公开(公告)号：US06779143B2

公开(公告)日：2004-08-17

申请号：US09898462

申请日：2001-07-05

申请人： Richard Roy Grisenthwaite

发明人： Richard Roy Grisenthwaite

IPC分类号： G01R3128

CPC分类号： G01R31/318555

摘要： An integrated circuit (2) is provided with a serial test scan chain (10) for testing proper operation. Asynchronous reset signal operation may be tested by using a reset signal generating scan chain cell (20) that is adapted such that a reset signal value held within a latch (14) of that cell is asynchronously gated to be applied to the circuit portion (8) under test by the scan enable signal. The latches (12) within the circuit portion under test that are forced to predetermine values by the correct operation of the reset may be preloaded with opposite sense values prior to the reset test.

摘要翻译： 集成电路（2）具有用于测试正确操作的串行测试扫描链（10）。 可以通过使用重置信号产生扫描链单元（20）来测试异步复位信号操作，所述复位信号生成扫描链单元（20）适于使得保持在该单元的锁存器（14）内的复位信号值异步地选通以施加到电路部分（8） ）由扫描使能信号进行测试。 被测电路部分内被迫通过正确的复位操作来预先确定值的锁存器（12）可以在复位测试之前用相反的检测值预加载。