Combustion detecting apparatus of engine
    101.
    发明授权
    Combustion detecting apparatus of engine 失效
    发动机燃烧检测装置

    公开(公告)号:US06739181B2

    公开(公告)日:2004-05-25

    申请号:US10261783

    申请日:2002-10-02

    申请人: Takayoshi Honda

    发明人: Takayoshi Honda

    IPC分类号: G01M1500

    摘要: An apparatus for determining combustion condition of engine detects ion current flowing in a spark plug. The apparatus samples the ion current by carrying out A/D conversion at every constant time period. The apparatus stores a maximum value of A/D converted values as a peak hold value. The apparatus further detects and stores that the ion current traverses a reference voltage during the A/D conversion time period. The apparatus clears the peak hold value, if the ion current traverses the reference voltage. The apparatus determines the combustion condition based on the peak hold value which has not been cleared continuously over a predetermined number of times of the A/D conversion. It is possible to reduce influence of noise.

    摘要翻译: 用于确定发动机燃烧状态的装置检测在火花塞中流动的离子电流。 该设备通过在每个恒定时间段进行A / D转换来对离子电流进行采样。 该装置将A / D转换值的最大值存储为峰值保持值。 该装置进一步检测并存储在A / D转换时间周期期间离子电流横穿参考电压。 如果离子电流穿过参考电压,器件将清除峰值保持值。 该装置基于在预定次数的A / D转换中连续清零的峰值保持值来确定燃烧条件。 可以减少噪音的影响。

    DMA control apparatus for multi-byte serial-bit transfer in a
predetermined byte pattern and between memories associated with
different asynchronously operating processors for a distributed system
    102.
    发明授权
    DMA control apparatus for multi-byte serial-bit transfer in a predetermined byte pattern and between memories associated with different asynchronously operating processors for a distributed system 失效
    用于以预定字节模式进行多字节串行比特传输的DMA控制装置,以及与用于分布式系统的不同异步操作处理器相关联的存储器之间的DMA控制装置

    公开(公告)号:US6115757A

    公开(公告)日:2000-09-05

    申请号:US833005

    申请日:1997-04-04

    申请人: Takayoshi Honda

    发明人: Takayoshi Honda

    CPC分类号: G06F13/28

    摘要: A DMA control apparatus transfers a data set of bytes, with no intermixing these data bytes and with favorable efficiency. A DMA controller receives data bytes serially and writes this data to a RAM. At this time, when the serially sent data are taken to be made up of data sets where one information item is formed of two bytes, the DMA controller, while temporarily storing data received in odd-numbered order in a data-set adjusting register, controls block write of this together with data received in even-numbered order to the RAM. Due to this, access where data other than these data sets is intermixed is eliminated, even in a case where asynchronous word-unit access of the RAM is performed by the CPU.

    摘要翻译: DMA控制装置传送数据字节集,不混合这些数据字节并且有效率。 DMA控制器串行接收数据字节,并将该数据写入RAM。 此时,当串行发送的数据由数据组构成,其中一个信息项由两个字节形成时,DMA控制器在临时存储以奇数次序接收的数据在数据集调整寄存器中时, 控制块的写入以及以偶数顺序接收的数据到RAM中。 由此,即使在由CPU执行RAM的异步字单位访问的情况下,也消除了与这些数据集之外的数据混合的访问。