公开(公告)号：US11961889B2

公开(公告)日：2024-04-16

申请号：US17951058

申请日：2022-09-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/41 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/41775 ,  H01L29/0607 ,  H01L29/401 ,  H01L29/66462 ,  H01L29/7786

Abstract: A semiconductor device includes a substrate, a semiconductor channel layer, a semiconductor barrier layer, a gate electrode, a first electrode, and a dielectric layer. The semiconductor channel layer is disposed on the substrate, and the semiconductor barrier layer is disposed on the semiconductor channel layer. The gate electrode is disposed on the semiconductor barrier layer. The first electrode is disposed at one side of the gate electrode. The first electrode includes a body portion and a vertical extension portion. The body portion is electrically connected to the semiconductor barrier layer, and the bottom surface of the vertical extension portion is lower than the top surface of the semiconductor channel layer. The dielectric layer is disposed between the vertical extension portion and the semiconductor channel layer.

公开(公告)号：US20240072153A1

公开(公告)日：2024-02-29

申请号：US18506101

申请日：2023-11-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang ,  Hsun-Wen Wang

IPC: H01L29/66 ,  H01L29/778

CPC classification number: H01L29/66431 ,  H01L29/7786

Abstract: A method for forming a high electron mobility transistor includes the steps of providing a substrate, forming a channel layer, a barrier layer, and a first passivation layer sequentially on the substrate, forming a plurality of trenches through at least a portion of the first passivation layer, forming a second passivation layer on the first passivation layer and covering along sidewalls and bottom surfaces of the trenches, and forming a conductive plate structure on the second passivation layer and filling the trenches.

公开(公告)号：US20230317840A1

公开(公告)日：2023-10-05

申请号：US18206620

申请日：2023-06-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66 ,  H01L29/47 ,  H01L21/285 ,  H01L29/205 ,  H01L29/423

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/475 ,  H01L21/28581 ,  H01L29/205 ,  H01L29/42376 ,  H01L29/42372 ,  H01L29/4238

Abstract: An HEMT includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer is different from that of the second III-V compound layer. A gate is disposed on the second III-V compound layer. The gate includes a first P-type III-V compound layer, an undoped III-V compound layer and an N-type III-V compound layer are deposited from bottom to top. The first P-type III-V compound layer, the undoped III-V compound layer, the N-type III-V compound layer and the first III-V compound layer are chemical compounds formed by the same group III element and the same group V element. A drain electrode is disposed at one side of the gate. A drain electrode is disposed at another side of the gate. A gate electrode is disposed directly on the gate.

公开(公告)号：US20230231022A1

公开(公告)日：2023-07-20

申请号：US17827994

申请日：2022-05-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/40 ,  H01L29/778 ,  H01L29/66 ,  H01L21/3115

CPC classification number: H01L29/408 ,  H01L29/7786 ,  H01L29/66462 ,  H01L21/31155

Abstract: A high electron mobility transistor (HEMT) includes a buffer layer on a substrate, a barrier layer on the buffer layer, a p-type semiconductor layer on the barrier layer, a first layer adjacent to a first side of the p-type semiconductor layer without extending to a second side of the p-type semiconductor layer, and a second layer adjacent to the second side of the p-type semiconductor layer without extending to the first side of the p-type semiconductor layer.

公开(公告)号：US11658223B2

公开(公告)日：2023-05-23

申请号：US17073410

申请日：2020-10-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/792 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/4234 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor structure includes a substrate, an insulating layer disposed on the substrate, an active layer disposed on the insulating layer, a first semiconductor device formed in a first device region of the active layer, a charge trap structure through the active layer and surrounding the first device region, and a charge trap layer between the insulating layer and the substrate and extending laterally to underlie the first device region and the charge trap structure.

公开(公告)号：US20230113989A1

公开(公告)日：2023-04-13

申请号：US18081646

申请日：2022-12-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/40 ,  H01L29/778 ,  H01L29/66

Abstract: A semiconductor device includes a substrate, a semiconductor channel layer, a semiconductor barrier layer, a gate electrode, a first electrode, a second electrode, a first dielectric layer and a second dielectric layer. The semiconductor channel layer is disposed on the substrate. The semiconductor barrier layer is disposed on the semiconductor channel layer. The gate electrode is disposed on the semiconductor barrier layer. The first electrode is disposed at one side of the gate electrode. The first electrode includes a body portion and a vertical extension portion. The second electrode is disposed at another side of the gate electrode. The second electrode includes a body portion and a vertical extension portion. The first dielectric layer is disposed between the vertical extension portion of the first electrode and the semiconductor channel layer. The second dielectric layer is disposed between the vertical extension portion of the second electrode and the semiconductor channel layer.

公开(公告)号：US20230079155A1

公开(公告)日：2023-03-16

申请号：US17990749

申请日：2022-11-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/423 ,  H01L29/786 ,  H01L27/092

Abstract: A manufacturing method of a semiconductor device includes the following steps. A first transistor is formed on a substrate. The first transistor includes a first semiconductor channel structure and two first source/drain structures. The first semiconductor channel structure includes first horizontal portions and a first vertical portion. The first horizontal portions are stacked in a vertical direction and separated from one another. Each of the first horizontal portions is elongated in a horizontal direction. The first vertical portion is elongated in the vertical direction and connected with the first horizontal portions. The two first source/drain structures are disposed at two opposite sides of each of the first horizontal portions in the horizontal direction respectively. The two first source/drain structures are connected with the first horizontal portions.

公开(公告)号：US20230024802A1

公开(公告)日：2023-01-26

申请号：US17955526

申请日：2022-09-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/40 ,  H01L29/778 ,  H01L29/66

Abstract: A semiconductor device includes a substrate, a semiconductor channel layer, a semiconductor barrier layer, a gate electrode, a first electrode, and a dielectric layer. The semiconductor channel layer is disposed on the substrate, and the semiconductor barrier layer is disposed on the semiconductor channel layer. The gate electrode is disposed on the semiconductor barrier layer. The first electrode is disposed at one side of the gate electrode. The first electrode includes a body portion and a vertical extension portion. The body portion is electrically connected to the semiconductor barrier layer, and the bottom surface of the vertical extension portion is lower than the top surface of the semiconductor channel layer. The dielectric layer is disposed between the vertical extension portion and the semiconductor channel layer. The first electrode is a conformal layer covers the semiconductor barrier layer and the dielectric layer.

公开(公告)号：US11562974B2

公开(公告)日：2023-01-24

申请号：US17160332

申请日：2021-01-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L23/00

Abstract: A hybrid bonding structure includes a first conductive structure and a second conductive structure. The first conductive structure includes a first conductive layer. A first barrier surrounds the first conductive layer. A first air gap surrounds and contacts the first barrier. A first dielectric layer surrounds and contacts the first air gap. The second conductive structure includes a second conductive layer. A second barrier contacts the second conductive layer. A second dielectric layer surrounds the second barrier. The second conductive layer bonds to the first conductive layer. The first dielectric layer bonds to the second dielectric layer.

公开(公告)号：US20230013358A1

公开(公告)日：2023-01-19

申请号：US17951058

申请日：2022-09-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/40 ,  H01L29/778 ,  H01L29/66

Abstract: A semiconductor device includes a substrate, a semiconductor channel layer, a semiconductor barrier layer, a gate electrode, a first electrode, and a dielectric layer. The semiconductor channel layer is disposed on the substrate, and the semiconductor barrier layer is disposed on the semiconductor channel layer. The gate electrode is disposed on the semiconductor barrier layer. The first electrode is disposed at one side of the gate electrode. The first electrode includes a body portion and a vertical extension portion. The body portion is electrically connected to the semiconductor barrier layer, and the bottom surface of the vertical extension portion is lower than the top surface of the semiconductor channel layer. The dielectric layer is disposed between the vertical extension portion and the semiconductor channel layer.