公开(公告)号：US06229749B1

公开(公告)日：2001-05-08

申请号：US09574678

申请日：2000-05-17

申请人： Timothy B. Cowles ,  Jeffrey P. Wright ,  Hua Zheng

发明人： Timothy B. Cowles ,  Jeffrey P. Wright ,  Hua Zheng

IPC分类号： G11C800

CPC分类号： G11C11/406

摘要： A self refresh decoder generates a self refresh command as long as the clock enable signal transitions low within a predetermined latency period after an auto refresh command is generated. As a result, an SDRAM is able to enter the self refresh mode even though the clock enable control signal differentiating the auto refresh command from the self refresh command is excessively delayed beyond the other control signals corresponding to both the auto refresh and the self refresh commands. The self refresh decoder includes a counter that is preloaded with a latency value and decrements to a terminal count responsive to the auto refresh command to terminate the latency period. The output of the counter is decoded to provide an enable signal as long as the terminal count has not been reached. As long as the enable signal is present, the self refresh command is generated responsive to receipt of the clock enable signal.

公开(公告)号：US6144593A

公开(公告)日：2000-11-07

申请号：US387650

申请日：1999-09-01

申请人： Timothy B. Cowles ,  Victor Wong ,  James S. Cullum ,  Jeffrey P. Wright

发明人： Timothy B. Cowles ,  Victor Wong ,  James S. Cullum ,  Jeffrey P. Wright

IPC分类号： G11C11/413 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/808

摘要： A semiconductor memory device including a memory-cell array divided into a plurality of memory sub-arrays that are arranged into rows and columns of memory cells. Each of the sub-arrays have a limited number of redundant rows and columns to repair defective memory cells. The redundant memory of at least two memory sub-arrays are coupled to an I/O line through a respective isolation circuit. A control circuit coupled to the isolation circuits selectively couples the redundant memory of the sub-arrays to the I/O line. Coupling the redundant memory of multiple sub-arrays facilitates using the redundant memory of one sub-array to repair the defective memory cells in other sub-arrays also coupled to the I/O line, when the redundant memory primarily associated with the other sub-arrays have been depleted.

摘要翻译： 一种半导体存储器件，包括被划分成存储器单元的行和列的多个存储器子阵列的存储单元阵列。 每个子阵列具有有限数量的冗余行和列来修复有缺陷的存储单元。 至少两个存储器子阵列的冗余存储器通过相应的隔离电路耦合到I / O线。 耦合到隔离电路的控制电路选择性地将子阵列的冗余存储器耦合到I / O线。 耦合多个子阵列的冗余存储器有助于使用一个子阵列的冗余存储器来修复也耦合到I / O线的其他子阵列中的有缺陷的存储器单元，当主要与其他子阵列相关联的冗余存储器时， 阵列已经耗尽。

公开(公告)号：US5999481A

公开(公告)日：1999-12-07

申请号：US918614

申请日：1997-08-22

申请人： Timothy B. Cowles ,  Jeffrey P. Wright ,  Hua Zheng

发明人： Timothy B. Cowles ,  Jeffrey P. Wright ,  Hua Zheng

IPC分类号： G11C11/406 ,  G11C7/00

CPC分类号： G11C11/406

摘要： A self refresh decoder generates a self refresh command as long as the clock enable signal transitions low within a predetermined latency period after an auto refresh command is generated. As a result, an SDRAM is able to enter the self refresh mode even though the clock enable control signal differentiating the auto refresh command from the self refresh command is excessively delayed beyond the other control signals corresponding to both the auto refresh and the self refresh commands. The self refresh decoder includes a counter that is preloaded with a latency value and decrements to a terminal count responsive to the auto refresh command to terminate the latency period. The output of the counter is decoded to provide an enable signal as long as the terminal count has not been reached. As long as the enable signal is present, the self refresh command is generated responsive to receipt of the clock enable signal.