公开(公告)号：US06636244B1

公开(公告)日：2003-10-21

申请号：US09395394

申请日：1999-09-13

申请人： Edward E. Kelley ,  Eric Michael Motika ,  Franco Motika

发明人： Edward E. Kelley ,  Eric Michael Motika ,  Franco Motika

IPC分类号： G09G500

CPC分类号： G06F3/04842

摘要： A method and computer program capable of providing a plurality of activation areas in a display, the display having a plurality of selectable objects surrounded by an object area which defines the boundaries of the selectable objects which must be contacted by a pointing device for selection. The activation areas surround the selectable objects and expand the boundary of the selectable objects which must be contacted by the pointing device for selection. The size of the activation areas is determined by an expansion boundary having a border that outlines the size and shape of the activation areas and enlarges the activation areas to a maximum size without overlapping.

摘要翻译： 一种能够在显示器中提供多个激活区域的方法和计算机程序，所述显示器具有由限定可选对象的边界的对象区域所围绕的多个可选择对象，所述对象区域必须由指示设备接触以供选择。 激活区域围绕可选对象并且扩展可选对象的边界，该对象必须由指示设备联系以进行选择。 激活区域的大小由具有概述激活区域的大小和形状的边界的扩展边界确定，并且将激活区域扩大到最大尺寸而不重叠。

公开(公告)号：US5807763A

公开(公告)日：1998-09-15

申请号：US851142

申请日：1997-05-05

申请人： Franco Motika ,  Paul Motika ,  Phil Nigh

发明人： Franco Motika ,  Paul Motika ,  Phil Nigh

IPC分类号： G01R31/28 ,  G01R31/312 ,  H01L21/66

CPC分类号： G01R31/312 ,  G01R31/2851

摘要： The manufacture of an integrated circuit chip includes testing the integrated circuit while an external electric field is applied to the integrated circuit to facilitate detection of open circuit type defects. The electric field may be provided by applying a high potential to a plate parallel to a plane of the integrated circuit or by applying a high potential to a probe and moving the probe across the surface of the integrated circuit chip to obtain information regarding the location of the defect. Use of a probe type electric field generator allows the approximate position of the defect to be determined. The invention enhances current testing and diagnostics methods for wafers, chips, and integrated circuit packages by allowing detection of floating net defects during other conventional tests.

公开(公告)号：US5640402A

公开(公告)日：1997-06-17

申请号：US569389

申请日：1995-12-08

申请人： Franco Motika ,  Donato Orazio Forlenza ,  Adrian Charles Anderson

发明人： Franco Motika ,  Donato Orazio Forlenza ,  Adrian Charles Anderson

IPC分类号： G01R31/3185 ,  G01R31/28

CPC分类号： G01R31/318555

摘要： A method of effectively reducing a length of shift register (SR) latches used in scan design testing for testing macro structures embedded within very large logic structures eliminates tester hardware buffer limitations required to load and unload a long chain SR. A plurality of shift register latches are connectable in a chain for scan design testing. Each shift register latch is composed of an L1 and an L2 latch receiving A and B clocks, respectively, to shift data into and out of the shift register latch. First specific shift register latches in a chain of shift register latches are used to generate test data inputs to an embedded macro structure, second specific shift register latches in the chain of shift register latches are used to receive test data outputs from the embedded macro structure. A separate B' clock is applied to the L2 latches of the first and second specific shift register latches while maintaining the B clock for the L2 latches for other shift register latches in the chain. The B' clock is similar to the B clock but displaced in time. The chain of shift register latches is flushed prior to a load operation of data for testing the embedded macro structure by simultaneously pulsing the A and B clocks. Then the embedded macro structure is loaded from the L2 latches of the first specific shift register latches with the L1 latches of the second specific shift register latches being loaded from the embedded macro structure by pulsing the B' clock to produce a scan cycle for the embedded macro structure.

摘要翻译： 一种有效减少扫描设计测试中使用的移位寄存器（SR）锁存器长度的方法，用于测试嵌入在非常大的逻辑结构中的宏结构，从而消除了加载和卸载长链SR所需的测试仪硬件缓冲区限制。 多个移位寄存器锁存器可连接在用于扫描设计测试的链中。 每个移位寄存器锁存器分别由接收A和B时钟的L1和L2锁存器组成，以将数据移入和移出移位寄存器锁存器。 移位寄存器锁存器中的第一个具体移位寄存器锁存器用于产生到嵌入式宏结构的测试数据输入，移位寄存器锁存链中的第二个特定移位寄存器锁存器用于从嵌入式宏结构接收测试数据输出。 单独的B'时钟被施加到第一和第二特定移位寄存器锁存器的L2锁存器，同时保持链锁中其他移位寄存器锁存器的L2锁存器的B时钟。 B时钟类似于B时钟，但是在时间上移位。 移位寄存器锁存链在用于测试嵌入式宏结构的数据的加载操作之前被刷新，同时脉冲A和B时钟。 然后从第一特定移位寄存器锁存器的L2锁存器加载嵌入式宏结构，其中第二特定移位寄存器锁存器的L1锁存器通过脉冲B'时钟从嵌入式宏结构加载以产生嵌入的扫描周期 宏观结构。

公开(公告)号：US08875261B2

公开(公告)日：2014-10-28

申请号：US12256129

申请日：2008-10-22

申请人： Wayne M. Delia ,  Edward E. Kelley ,  Franco Motika

发明人： Wayne M. Delia ,  Edward E. Kelley ,  Franco Motika

IPC分类号： G06F15/16 ,  G06F12/14 ,  G06F21/31

CPC分类号： H04L63/20 ,  G06F21/31 ,  H04L63/083 ,  H04L63/0846

摘要： A rules driven multiple passwords system is provided wherein a list of stored passwords are used in rotation over time in accordance with a set of rules or conditions managed by the system. With such an arrangement, the currently active password of a system User may automatically be changed, in accordance with the rules or conditions, to the next password in the list. The User is notified as to the newly assigned password.

摘要翻译： 提供了一种规则驱动的多密码系统，其中根据由系统管理的一组规则或条件，随着时间的推移使用所存储密码的列表。 通过这样的安排，系统用户的当前活动密码可以根据规则或条件自动地改变到列表中的下一个密码。 通知用户新分配的密码。

公开(公告)号：US08791822B2

公开(公告)日：2014-07-29

申请号：US12027540

申请日：2008-02-07

申请人： Wayne M. Delia ,  Edward E. Kelley ,  Franco Motika

发明人： Wayne M. Delia ,  Edward E. Kelley ,  Franco Motika

IPC分类号： G08B13/14

CPC分类号： G07D7/01

摘要： A system and method of determining likelihood of counterfeiting without inspection of currency compares signals returned by uniquely customized RFID chips when interrogated, preferably incident to a transaction. The RFID information is compared to RFID information for bills known to be in circulation in order to validate a given currency bill. Usage patterns can be determined from statistical analysis of such reports and reported usage patterns will statistically differ significantly if not radically with the number of RFID chips returning the same RFID information and such differences will increase in either or both of geographic locations of reports and frequency of reports with increase of the number of bills having duplicated RFID chips. The basic infrastructure for practice of the invention is also capable of tracking genuine currency following, for example, a theft or other criminal activity.

摘要翻译： 在不检查货币的情况下确定伪造可能性的系统和方法比较了由特制定制的RFID芯片在询问时返回的信号，优选事件事件发生在交易中。 将RFID信息与已知流通的票据的RFID信息进行比较，以验证给定的货币票据。 使用模式可以从这样的报告的统计分析中确定，如果RFID芯片返回相同的RFID信息的数量不是很大，报告的使用模式将有统计上的显着差异，并且这些差异将在报告的地理位置和频率的两个或两个之间增加 报告说，具有复制的RFID芯片的钞票数量增加。 本发明实践的基本基础也能跟踪真实的货币，例如盗窃或其他犯罪活动。

公开(公告)号：US08712050B2

公开(公告)日：2014-04-29

申请号：US11853267

申请日：2007-09-11

申请人： Wayne M. Delia ,  Edward E. Kelley ,  Franco Motika

发明人： Wayne M. Delia ,  Edward E. Kelley ,  Franco Motika

IPC分类号： H04L9/00

CPC分类号： G06F3/023 ,  G06F21/83 ,  G06F21/85 ,  G06F2221/2107

摘要： A method of implementing dynamic pseudorandom keyboard remapping of a system including a keyboard in communication with an operating system of a computing device includes encrypting an original keyboard scan code corresponding to each of a plurality of keyboard keys, using a mapping algorithm, wherein the mapping algorithm encrypts the original keyboard scan code by using both the original keyboard scan code and a current one of a sequence of pseudorandom numbers generated using a pseudorandom number generator (PRNG) algorithm and an initial seed value; and decrypting the original keyboard scan code based on an encrypted scan code generated and transmitted from the keyboard to the operating, responsive to a keystroke of the keyboard, wherein the operating system also uses the mapping algorithm, the PRNG algorithm, and the initial seed value.

摘要翻译： 实现包括与计算设备的操作系统通信的键盘的系统的动态伪随机键盘重新映射的方法包括使用映射算法对与多个键盘键中的每一个对应的原始键盘扫描码进行加密，其中映射算法 通过使用原始键盘扫描码和使用伪随机数生成器（PRNG）算法和初始种子值生成的伪随机数的序列中的当前一个来加密原始键盘扫描码; 以及基于从所述键盘产生并从所述键盘发送到所述操作的加密扫描码，将所述原始键盘扫描码解密，以响应于所述键盘的击键，其中所述操作系统还使用所述映射算法，所述PRNG算法和所述初始种子值 。

公开(公告)号：US08712049B2

公开(公告)日：2014-04-29

申请号：US11853263

申请日：2007-09-11

申请人： Wayne M. Delia ,  Edward E. Kelley ,  Franco Motika

发明人： Wayne M. Delia ,  Edward E. Kelley ,  Franco Motika

IPC分类号： H04L9/00

CPC分类号： G06F21/83

摘要： A system for implementing dynamic pseudorandom keyboard remapping includes a keyboard in communication with an operating system of a computing device; the keyboard configured to encrypt an original keyboard scan code corresponding to each of a plurality of keyboard keys, using a mapping algorithm, wherein the mapping algorithm encrypts the original keyboard scan code by using both the original keyboard scan code and a current one of a sequence of pseudorandom numbers generated using a pseudorandom number generator (PRNG) algorithm and an initial seed value; and the operating system configured to decrypt the original keyboard scan code based on an encrypted scan code generated and transmitted from the keyboard thereto, responsive to a keystroke of the keyboard, wherein the operating system also uses the mapping algorithm, the PRNG algorithm, and the initial seed value.

摘要翻译： 用于实现动态伪随机键盘重新映射的系统包括与计算设备的操作系统通信的键盘; 所述键盘被配置为使用映射算法加密与多个键盘键中的每一个相对应的原始键盘扫描码，其中，所述映射算法通过使用原始键盘扫描码和序列中的当前一个键盘扫描码来加密原始键盘扫描码 使用伪随机数生成器（PRNG）算法和初始种子值生成伪随机数; 以及所述操作系统，其被配置为响应于所述键盘的击键，基于从所述键盘向其生成和发送的加密扫描码来解密所述原始键盘扫描码，其中所述操作系统还使用所述映射算法，所述PRNG算法和 初始种子值。

公开(公告)号：US20120096314A1

公开(公告)日：2012-04-19

申请号：US12904205

申请日：2010-10-14

申请人： Franco Motika ,  John D. Parker

发明人： Franco Motika ,  John D. Parker

IPC分类号： G06F11/27 ,  G06F11/30

CPC分类号： G06F11/2242 ,  G06F11/27

摘要： Exemplary embodiments include a sequential and concurrent status detection and evaluation method for multiple processor cores, including receiving data from a plurality of processor cores, for each of the plurality of processor cores, simultaneously running a built-in self test to determine if each of the plurality of cores has failed, checking the data for a dominant logic state and recording a subset of the plurality of processor cores that have failed.

摘要翻译： 示例性实施例包括用于多个处理器核的顺序和并发状态检测和评估方法，包括从多个处理器核心接收数据，用于多个处理器核心中的每一个，同时运行内置自我测试以确定每个处理器核心 多个核心已经失败，检查数据以获得主导逻辑状态并记录已经失败的多个处理器核心的子集。

公开(公告)号：US08136082B2

公开(公告)日：2012-03-13

申请号：US13102249

申请日：2011-05-06

申请人： Rao H. Desineni ,  Maroun Kassab ,  Franco Motika ,  Leah Marie Pfeifer Pastel

发明人： Rao H. Desineni ,  Maroun Kassab ,  Franco Motika ,  Leah Marie Pfeifer Pastel

IPC分类号： G06F17/50 ,  G06F11/22 ,  G06F19/00

CPC分类号： G01R31/31835

摘要： A method of testing an integrated circuit. The method includes selecting a set of physical features of nets and devices of the integrated circuit, the integrated circuit having pattern input points and pattern observation points connected by the nets, each of the nets defined by an input point and all fan out paths to (i) input points of other nets of the nets or (ii) to the pattern observation points; selecting a measurement unit for each feature of the set of features; assigning a weight to each segment of each fan out path based on a number of the measurement units of the feature in each segment of each fan out path of each of the nets; and generating a set of test patterns optimized for test-coverage and cost based on the weights assigned to each segment of each of the nets of the integrated circuit.

摘要翻译： 一种集成电路测试方法。 该方法包括选择集成电路的网络和设备的一组物理特征，集成电路具有由网络连接的模式输入点和模式观察点，每个网络由输入点定义，并且所有扇出路径到（ i）网的其他网的输入点或（ii）到模式观察点; 为特征集合中的每个特征选择测量单元; 基于每个网络的每个扇出路径的每个段中的特征的测量单元的数量，为每个扇出路径的每个段分配权重; 以及基于分配给集成电路的每个网络的每个段的权重，生成针对测试覆盖和成本优化的一组测试模式。

公开(公告)号：US07845005B2

公开(公告)日：2010-11-30

申请号：US11307429

申请日：2006-02-07

申请人： Edward E. Kelley ,  Franco Motika ,  Tijs I. Wilbrink

发明人： Edward E. Kelley ,  Franco Motika ,  Tijs I. Wilbrink

IPC分类号： G06F12/14

CPC分类号： G06F21/53 ,  G06F21/565 ,  G06F21/566 ,  G06F2221/2149

摘要： A computer random access memory is divided into first and second partitions. Each partition has its own operating system (OS). The first partition has a conventional OS and is designated for non-Internet use. The second partition is designated for secure Internet access, and has an OS specific for Internet usage. Software in the second partition cannot write or copy files in the second partition. The size of the second partition is fixed and unchangeable while said second partition is open. Each software application in the second partition is allocated a memory region that cannot be changed, thereby preventing memory overflow attacks. A secure memory is designated for temporary storage of software used in the second partition. Cyclic redundancy check (CRC) values are calculated for all files in the secure memory. To detect unauthorized file changes, CRC values are calculated for all files used in the second partition, and checked against values stored in the secure memory. The second partition can write only to a secure memory using a security arrangement such as password protection or a download memory separate from the first partition to allow files stored in the download memory to be examined by scanning and testing from the first partition prior to being stored elsewhere in the computer.

摘要翻译： 计算机随机存取存储器被分成第一和第二分区。 每个分区都有自己的操作系统（OS）。 第一个分区具有常规操作系统，并被指定用于非互联网使用。 第二个分区被指定用于安全的Internet访问，并且具有专用于因特网使用的操作系统。 第二个分区中的软件无法在第二个分区中写入或复制文件。 第二分区的大小是固定的，并且在所述第二分区打开时不可改变。 第二分区中的每个软件应用程序都被分配一个无法更改的内存区域，从而防止内存溢出攻击。 指定用于在第二分区中使用的软件的临时存储的安全存储器。 针对安全存储器中的所有文件计算循环冗余校验（CRC）值。 要检测未经授权的文件更改，将对第二个分区中使用的所有文件计算CRC值，并对存储在安全存储器中的值进行检查。 第二分区可以使用诸如密码保护的安全布置或与第一分区分离的下载存储器仅写入安全存储器，以允许通过在存储之前从第一分区进行扫描和测试来检查存储在下载存储器中的文件 电脑里的其他地方