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    Semiconductor integrated circuit device having an internal voltage generation circuit layout easily adaptable to change in specification
    111.
    发明授权
    Semiconductor integrated circuit device having an internal voltage generation circuit layout easily adaptable to change in specification 失效
    具有容易适应规格变化的内部电压发生电路布局的半导体集成电路器件

    公开(公告)号：US06519191B1

    公开(公告)日：2003-02-11

    申请号：US09696011

    申请日：2000-10-26

    申请人： Fukashi Morishita

    发明人： Fukashi Morishita

    IPC分类号： G11C700

    CPC分类号： G11C5/14 ,  G11C5/145 ,  G11C5/147

    摘要： An active down converting supplying a large current consumed when a memory array is active, and a Vpp pump for generating a boosted voltage are configured into active units as cells. A required number of active units are provided depending on the array structure and the operation conditions. A power supply circuit can be redesigned and/or rearranged within a short period for adaptation to change in internal structure for the memory array.

    摘要翻译： 当存储器阵列处于活动状态时，提供消耗的大电流的有效下变频器和用于产生升压电压的Vpp泵被配置为有源单元作为单元。 根据阵列结构和操作条件，提供所需数量的有效单元。 电源电路可以在短时间内重新设计和/或重新布置，以适应存储器阵列的内部结构的改变。

    Semiconductor memory provided with data-line equalizing circuit
    112.
    发明授权
    Semiconductor memory provided with data-line equalizing circuit 失效
    半导体存储器配有数据线均衡电路

    公开(公告)号：US06373763B1

    公开(公告)日：2002-04-16

    申请号：US09839403

    申请日：2001-04-23

    申请人： Yasuhiko Taito ,  Akira Yamazaki ,  Fukashi Morishita ,  Nobuyuki Fujii ,  Mako Okamoto

    发明人： Yasuhiko Taito ,  Akira Yamazaki ,  Fukashi Morishita ,  Nobuyuki Fujii ,  Mako Okamoto

    IPC分类号： G11C700

    CPC分类号： G11C7/12 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4094

    摘要： An equalizing circuit includes a plurality of N-channel MOS transistors for respectively setting a data line to a predetermined precharge voltage. The H-level voltage Vddb of a control signal for turning on these N-channel MOS transistors is set to a range higher than the sum of the precharge voltage and a transistor threshold voltage. A Vddb generation circuit steps up an external power-supply voltage and sets a voltage Vddb in a range lower than a step-up voltage for activating a word line.

    摘要翻译： 均衡电路包括用于分别将数据线设置为预定预充电电压的多个N沟道MOS晶体管。 用于接通这些N沟道MOS晶体管的控制信号的H电平电压Vddb被设置为高于预充电电压和晶体管阈值电压之和的范围。 Vddb生成电路升高外部电源电压，并将电压Vddb设置在低于用于激活字线的升压电压的范围内。