公开(公告)号：US20020020858A1

公开(公告)日：2002-02-21

申请号：US09918208

申请日：2001-07-30

Applicant: Intersil Americas Inc,

Inventor： Brent R. Doyle

IPC: H01L027/10 ,  H01L029/76 ,  H01L029/94 ,  H01L031/062 ,  H01L031/113 ,  H01L031/119

CPC classification number: H01L27/0921

Abstract: A junction isolated Complementary Metal Oxide Semiconductor (CMOS) transistor device includes a substrate of a first conductivity type and first and second buried layers formed within the substrate and having a second conductivity type opposite from the first conductivity type. First and second well regions of respective first and second conductivity are formed above respective first and second buried layers. An NMOS transistor and PMOS transistor are formed in the respective first and second well regions. The buried layer of the NMOS transistor is at nullV (typically ground) and the buried layer of the PMOS transistor is biased at a positive supply voltage and spaced sufficiently from the NMOS transistor to improve single event effects occurrence.

Abstract translation: 接合隔离的互补金属氧化物半导体（CMOS）晶体管器件包括第一导电类型的衬底和形成在衬底内并具有与第一导电类型相反的第二导电类型的第一和第二掩埋层。 各自的第一和第二导电性的第一和第二阱区形成在相应的第一和第二埋层之上。 在相应的第一和第二阱区域中形成NMOS晶体管和PMOS晶体管。 NMOS晶体管的掩埋层处于-V（通常接地），并且PMOS晶体管的掩埋层被偏置在正电源电压并且与NMOS晶体管充分隔开以改善单个事件效应的出现。