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公开(公告)号:US20240243129A1
公开(公告)日:2024-07-18
申请号:US18622142
申请日:2024-03-29
发明人: Chien Yao Huang , Yu-Ti Su
IPC分类号: H01L27/092 , H01L21/761 , H01L21/8238 , H01L29/10 , H01L21/74 , H01L29/78
CPC分类号: H01L27/0921 , H01L21/761 , H01L21/823892 , H01L29/1083 , H01L21/74 , H01L29/78
摘要: The present disclosure describes a metal-oxide-semiconductor field-effect transistor (MOSFET) device. The MOSFET device includes a first-type substrate, a deep-second-type well in the first-type substrate, a first-type well over the deep-second-type well, and a second-type well over the deep-second-type well. The second-type well and the deep-second-type well form an enclosed space that includes the first-type well. The MOSFET also includes an embedded semiconductor region (ESR) in a vicinity of the enclosed space. The ESR includes a dopant concentration lower than at least one of a dopant concentration of the first-type well, a dopant concentration of the second-type well, and a dopant concentration of the deep-second-type well.
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公开(公告)号:US12002800B2
公开(公告)日:2024-06-04
申请号:US17861544
申请日:2022-07-11
发明人: Chien-Yao Huang
IPC分类号: H01L27/02 , H01L27/06 , H01L27/092 , H01L29/06 , H01L29/08 , H01L29/735
CPC分类号: H01L27/0248 , H01L27/027 , H01L27/0629 , H01L27/067 , H01L27/0921 , H01L29/0619 , H01L29/0808 , H01L29/0821 , H01L29/735
摘要: A semiconductor device includes first to fifth regions, first and second resistive loads. The first region is coupled to a first reference voltage terminal. The first to third regions operate as a first transistor. The fourth region is coupled to a second reference voltage terminal. The fourth to fifth regions operate as a second transistor. The first resistive load couples the second region to the second reference voltage terminal. The second resistive load couples the fifth region to the first reference voltage terminal. The first, third, second, fifth and fourth regions are arranged in order, each of the first, second and third regions corresponds to a first conductive type, and each of the fourth and fifth regions corresponds to a second conductive type.
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公开(公告)号:US20240079408A1
公开(公告)日:2024-03-07
申请号:US18508015
申请日:2023-11-13
发明人: Yi-Feng CHANG , Po-Lin PENG , Jam-Wem LEE
IPC分类号: H01L27/092 , H01L21/8238 , H01L27/02 , H01L29/06 , H01L29/10 , H01L29/87
CPC分类号: H01L27/0921 , H01L21/823871 , H01L27/0262 , H01L29/0649 , H01L29/1083 , H01L29/87
摘要: A method includes the following operations: disconnecting at least one of drain regions that are formed on a first active area, of first transistors, from a first voltage; and disconnecting at least one of drain regions that are formed on a second active area, of second transistors coupled to the first transistors from a second voltage. The at least one of drain regions of the second transistors corresponds to the at least one of drain regions of the first transistors.
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公开(公告)号:US20230261003A1
公开(公告)日:2023-08-17
申请号:US18306508
申请日:2023-04-25
发明人: Chien Yao HUANG , Wun-Jie LIN , Kuo-Ji CHEN
IPC分类号: H01L27/118 , H01L27/02 , H01L27/092 , G06F30/392
CPC分类号: H01L27/11807 , H01L27/0207 , H01L27/0921 , G06F30/392 , G06F2119/06
摘要: An integrated circuit (IC) device includes a plurality of first doped regions of a first semiconductor type over at least one first well region of the first semiconductor type, and a second doped region of a second semiconductor type over a second well region of the second semiconductor type. The second semiconductor type is different from the first semiconductor type. The plurality of first doped regions is arranged along a first direction. Each of the plurality of first doped regions has a first length in the first direction. The second doped region extends in the first direction between at least two first doped regions among the plurality of first doped regions over a second length greater than the first length.
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5.
公开(公告)号:US20180040619A1
公开(公告)日:2018-02-08
申请号:US15729002
申请日:2017-10-10
IPC分类号: H01L27/092 , H01L29/06 , H01L21/762 , H01L21/74 , H01L21/768 , H01L21/8238 , H01L23/48
CPC分类号: H01L27/0921 , H01L21/743 , H01L21/76224 , H01L21/76898 , H01L21/823871 , H01L21/823878 , H01L21/823892 , H01L23/481 , H01L27/092 , H01L29/0649 , H01L2924/0002 , H01L2924/00
摘要: A method of manufacturing a semiconductor structure includes: forming a trench in a back side of a substrate; depositing a dopant on surfaces of the trench; forming a shallow trench isolation (STI) structure in a top side of the substrate opposite the trench; forming a deep well in the substrate; out-diffusing the dopant into the deep well and the substrate; forming an N-well and a P-well in the substrate; and filling the trench with a conductive material.
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公开(公告)号:US09793172B2
公开(公告)日:2017-10-17
申请号:US15298933
申请日:2016-10-20
IPC分类号: H01L21/425 , H01L21/8238 , H01L21/265 , H01L29/66 , H01L29/10 , H01L21/04 , H01L21/82 , H01L21/02 , H01L27/092 , H01L29/78
CPC分类号: H01L21/823892 , H01L21/02694 , H01L21/046 , H01L21/26506 , H01L21/8213 , H01L21/823878 , H01L27/0921 , H01L29/105 , H01L29/1083 , H01L29/66068 , H01L29/66537 , H01L29/6659 , H01L29/66651 , H01L29/7833
摘要: A method for fabricating field effect transistors using carbon doped silicon layers to substantially reduce the diffusion of a doped screen layer formed below a substantially undoped channel layer includes forming an in-situ epitaxial carbon doped silicon substrate that is doped to form the screen layer in the carbon doped silicon substrate and forming the substantially undoped silicon layer above the carbon doped silicon substrate. The method may include implanting carbon below the screen layer and forming a thin layer of in-situ epitaxial carbon doped silicon above the screen layer. The screen layer may be formed either in a silicon substrate layer or the carbon doped silicon substrate.
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公开(公告)号:US09786608B2
公开(公告)日:2017-10-10
申请号:US15164680
申请日:2016-05-25
IPC分类号: H01L31/115 , H01L21/20 , H01L23/552 , H01L21/18 , H01L27/092 , H01L21/263 , H01L21/265 , H01L21/304
CPC分类号: H01L23/552 , H01L21/187 , H01L21/263 , H01L21/26513 , H01L21/304 , H01L27/0921
摘要: A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device wafer and the handle wafer is used for making semiconductor devices. The improved doping profile of the bonded wafer structure is well suited for use in the manufacture of integrated circuits. The bonded wafer structure is especially suited for making radiation-hardened integrated circuits.
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公开(公告)号:US20170256542A1
公开(公告)日:2017-09-07
申请号:US15059516
申请日:2016-03-03
IPC分类号: H01L27/092 , H01L29/06 , H01L21/8238 , H01L29/66
CPC分类号: H01L21/2257 , H01L21/2255 , H01L21/2256 , H01L21/823807 , H01L21/823821 , H01L21/823892 , H01L27/0921 , H01L27/0924 , H01L29/0638 , H01L29/1083 , H01L29/16 , H01L29/66537 , H01L29/66803
摘要: A method for doping fins includes depositing a first dopant layer at a base of fins formed in a substrate, depositing a dielectric layer on the first dopant layer and etching the dielectric layer and the first dopant layer in a first region to expose the substrate and the fins. A second dopant layer is conformally deposited over the fins and the substrate in the first region. The second dopant layer is recessed to a height on the fins in the first region. An anneal is performed to drive dopants into the fins from the first dopant layer in a second region and from the second dopant layer in the first region to concurrently form punch through stoppers in the fins and wells in the substrate.
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公开(公告)号:US20170236822A1
公开(公告)日:2017-08-17
申请号:US15586285
申请日:2017-05-04
发明人: Yu-Cheng Tung
IPC分类号: H01L27/092 , H01L29/06 , H01L21/8238 , H01L29/10
CPC分类号: H01L27/0921 , H01L21/0243 , H01L21/02518 , H01L21/823821 , H01L21/823878 , H01L21/823892 , H01L27/0924 , H01L29/0607 , H01L29/0653 , H01L29/1083 , H01L29/66803
摘要: A semiconductor device includes: a substrate having a first region and a second region; a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; a first bump on the first region; a first doped layer on the first fin-shaped structure and the bump; and a gate structure covering the bump.
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公开(公告)号:US09685442B2
公开(公告)日:2017-06-20
申请号:US14885308
申请日:2015-10-16
发明人: Kazushi Fujita , Taiji Ema , Makoto Yasuda , Mitsuaki Hori
IPC分类号: H01L27/085 , H01L27/092 , H01L29/66 , H01L29/872 , H01L21/8238 , H01L29/36 , H01L29/78 , H01L29/861 , H01L29/06
CPC分类号: H01L27/0921 , H01L21/823892 , H01L27/0255 , H01L27/0928 , H01L29/0619 , H01L29/0649 , H01L29/36 , H01L29/66136 , H01L29/66143 , H01L29/78 , H01L29/7833 , H01L29/8613 , H01L29/872 , H01L29/8725
摘要: A semiconductor device including an insulating film in a first region of a semiconductor substrate; a first impurity region and a second impurity region of a first conductivity type, each of the regions including a part located deeper than the insulating film in contact with each other, and the insulating film being sandwiched by the first and second impurity regions in planar view in the first region of the semiconductor substrate; a metal silicide film on the first impurity region and in Schottky junction with the first impurity region; a first impurity of the first impurity region having a peak of a concentration profile deeper than a bottom of the insulating film; a second impurity of the second impurity region having a concentration higher than a concentration of the first impurity in a part of the first impurity region shallower than the bottom of the insulating film.
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