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公开(公告)号：US11456243B2
公开(公告)日：2022-09-27
申请号：US17080859
申请日：2020-10-27
IPC分类号： H01L23/498 , H01L23/00 , H01L25/18 , H01L21/56 , H01L21/683 , H01L25/065 , H01L25/16 , H01L25/00 , H01L23/31 , H01L23/538 , H01L21/48 , H01L23/24 , H01L21/78 , H01L23/16 , H01L23/367 , H01L23/552
摘要： A semiconductor package structure, including a circuit substrate, at least two chips, an encapsulant, and a redistribution layer, is provided. The circuit substrate has a first surface and a second surface opposite to the first surface. The at least two chips are disposed on the first surface. Each of the at least two chips has an active surface facing the circuit substrate and includes multiple first conductive connectors and multiple second conductive connectors disposed on the active surface. A pitch of the first conductive connectors is less than a pitch of the second conductive connectors. The encapsulant encapsulates the at least two chips. The redistribution layer is located on the second surface. The first conductive connectors are electrically connected to the redistribution layer by the circuit substrate. The second conductive connectors are electrically connected to the circuit substrate. A manufacturing method of a semiconductor package structure is also provided.
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公开(公告)号：US20220165709A1
公开(公告)日：2022-05-26
申请号：US17210452
申请日：2021-03-23
发明人： Yin-Huang KUNG , Chia-Hung LIN , Fu-Yuan YAO , Chun-Wu LIU
IPC分类号： H01L25/065 , H01L25/00
摘要： A stacked semiconductor package has a substrate, a first chip, at least one spacer, a second chip and an encapsulation. The first chip and the second chip are intersecting stacked on the substrate. The at least one spacer is stacked on the substrate to support the second chip. The encapsulation is formed to encapsulate the substrate, the first chip, the at least one spacer and the second chip. The at least one spacer is made of the material of the encapsulation. Therefore, the adhesion between the at least one spacer and the encapsulation is enhanced to avoid the delamination during the reliability test and enhances the reliability of the stacked semiconductor package.
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公开(公告)号：US20220148955A1
公开(公告)日：2022-05-12
申请号：US17198653
申请日：2021-03-11
发明人： Chih-Yen SU , Chun-Te Lin
IPC分类号： H01L23/498 , H01L23/31 , H01L23/00
摘要： A semiconductor package has a substrate, a chip and an encapsulation. The substrate has a dielectric layer, a copper wiring layer and a solder resist layer formed thereon. The copper wiring layer is formed on the dielectric layer and is covered by the solder resist layer. The solder resist layer has a chip area defined thereon and an annular opening formed thereon. The annular opening surrounds the chip area and exposes part of the copper wiring layer. The chip is mounted on the chip area and is encapsulated by the encapsulation. Therefore, the semiconductor package with the annular opening makes the solder resist layer discontinuous, and the concentration stress is decreased to avoid a crack formed on the solder resist layer or the copper wiring layer when doing thermal-cycle test.
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公开(公告)号：US20220118631A1
公开(公告)日：2022-04-21
申请号：US17183752
申请日：2021-02-24
发明人： Wu-Yi CHOU , Kun-Chi HSU , Chin-Ta WU , Yung-Chin SHIH , Chin Cheng LIU , Jentung TSENG
IPC分类号： B25J15/06 , H01L21/683
摘要： A head of chip picker is disclosed. The head has a clipping seat and an elastic block. The clipping seat has a body and two arms. The arms are respectively and downwardly extended from two opposite sides of an inner top surface of the body, so a cavity with a wide-top and narrow-bottom shape is constituted among the inner top surface and the arms. The elastic block matches the cavity and is laterally inserted into the cavity. The elastic block is not deformed after inserting into the cavity and provides a flat bottom surface.
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公开(公告)号：US11302539B2
公开(公告)日：2022-04-12
申请号：US16987470
申请日：2020-08-07
发明人： Tsung-Han Chiang , Chun-Te Lin
IPC分类号： H01L21/56 , H01L23/31 , H01L23/29 , H01L21/683
摘要： A method for packaging a semiconductor device includes the steps of: disposing a wafer on a first carrier plate; attaching a second carrier plate to a side of the first carrier plate opposite to the wafer; disposing a chip unit on a side of the wafer opposite to the first carrier plate; and covering the wafer and the chip unit with an encapsulation layer. A semiconductor packaging structure is also disclosed.
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公开(公告)号：US20220097891A1
公开(公告)日：2022-03-31
申请号：US17217207
申请日：2021-03-30
发明人： Yen Yu CHEN , Shin-Kung CHEN , Yuan-Jung LU , Hsing-Fu PENG
摘要： A manual labeling device is disclosed. The manual labeling device has a platform, a plurality of positioning elements and a pivoting device. The platform has a labeling area. The positioning elements are mounted on the platform and around the labeling area. The pivoting device is pivotally mounted on one side of the platform and has a pivot shaft and a pivot arm. The operator manually places one product in the labeling area of the platform and the product is fixed in the labeling area by the positioning elements. The operator only pivots the pivot arm and the pivot arm directly aligns with the labeling area. Therefore, it does not take times to align the tool and the labeling area before attaching the label and the label attaching task is simplified to increase the productivity and quality of labeling (units per hour; UPH).
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137.发明授权公开(公告)号：US11257747B2
公开(公告)日：2022-02-22
申请号：US16382229
申请日：2019-04-12
IPC分类号： H01L23/498 , H01L23/31 , H01L21/56 , H01L21/48 , H01L23/66
摘要： A semiconductor package including a semiconductor chip, a conductive element disposed aside the semiconductor chip, a conductive via disposed on and electrically connected to the conductive element, an insulating encapsulation, and a first circuit structure disposed on the semiconductor chip and the conductive via is provided. A height of the conductive element is less than a height of the semiconductor chip. The insulating encapsulation encapsulates the semiconductor chip, the conductive element, and the conductive via. The conductive via is located between the first circuit structure and the conductive element, and the semiconductor chip is electrically coupled to the conductive via through the first circuit structure.
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138.发明申请公开(公告)号：US20210365651A1
公开(公告)日：2021-11-25
申请号：US17037949
申请日：2020-09-30
发明人： Chi-Chung Yu , Kai-Hung LIN , Tien-Hung LOU
摘要： An identification method of an integrated circuit chip of the present invention includes identifying a surface structure or an internal structure of an integrated circuit chip, generating a structural information set according to the surface structure or internal structure, converting the structural information set into an identification information set. The identification information set generated by the above-mentioned identification method can be stored in a digital file, and a chip manufacturer requires no visible information printed on an outer surface of the integrated circuit chip such that factory information of the integrated circuit chip can be concealed. When retrieving the malfunctioned or defective integrated circuit chip, the manufacturer can acquire a new generated identification information set by identify the integrated circuit chip and compare the new generated identification information set and the generated identification information set stored in the file to obtain the factory information of the retrieved integrated circuit chip.
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公开(公告)号：US20210351044A1
公开(公告)日：2021-11-11
申请号：US16987470
申请日：2020-08-07
发明人： Tsung-Han CHIANG , Chun-Te LIN
IPC分类号： H01L21/56 , H01L21/683 , H01L23/29 , H01L23/31
摘要： A method for packaging a semiconductor device includes the steps of: disposing a wafer on a first carrier plate; attaching a second carrier plate to a side of the first carrier plate opposite to the wafer; disposing a chip unit on a side of the wafer opposite to the first carrier plate; and covering the wafer and the chip unit with an encapsulation layer. A semiconductor packaging structure is also disclosed.
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140.发明授权公开(公告)号：US11171106B2
公开(公告)日：2021-11-09
申请号：US16740496
申请日：2020-01-13
IPC分类号： H01L23/00 , H01L21/48 , H01L21/56 , H01L23/31 , H01L23/498
摘要： A semiconductor package structure including a circuit substrate, at least one chip, an encapsulant, a plurality of conductive connectors, a redistribution layer, and a plurality of conductive terminals is provided. The circuit substrate has a first surface and a second surface opposite to the first surface. The at least one chip has an active surface and a rear surface opposite to the active surface. The at least one chip is disposed on the circuit substrate with the rear surface. The encapsulant encapsulates the at least one chip. The plurality of conductive connectors surrounds the at least one chip. The redistribution layer is located on the encapsulant. The plurality of conductive terminals is located on the second surface. The at least one chip is electrically connected to the plurality of conductive terminals via the redistribution layer, the plurality of conductive connectors, and the circuit substrate. A manufacturing method of a semiconductor package structure is also provided.
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