公开(公告)号：US20210405928A1

公开(公告)日：2021-12-30

申请号：US17447520

申请日：2021-09-13

Applicant: Micron Technology, Inc.

Inventor： Luca Bert

IPC: G06F3/06

Abstract: A processing device in a memory system receives a request to read data stored on a first plane of a plurality of planes of a memory device while a plurality of write operations are ongoing, wherein each of the plurality of write operations are performed concurrently to write each of a plurality of single-plane segments of data to a corresponding plane of the plurality of planes of the memory device, and wherein a multi-plane segment of data received with a write request is divided into the plurality of single-plane segments of data. The processing device further suspends a first write operation of the plurality of write operations, the first write operation corresponding to the first plane, and performs a read operation to read the data stored on the first plane while continuing to perform at least one other write operation of the plurality of write operations corresponding to another plane of the plurality planes.

公开(公告)号：US20210124499A1

公开(公告)日：2021-04-29

申请号：US16663025

申请日：2019-10-24

Applicant: Micron Technology, Inc.

Inventor： Luca Bert

IPC: G06F3/06 ,  G06F9/48

Abstract: A processing device, operatively coupled with the memory device, is configured to provide a plurality of functions for accessing the memory device, wherein a function of the plurality of function receives input/output (I/O) operations from a host computing system. The processing device further determines a quality of service level of each function of the plurality of functions, and assigns to each function of the plurality of functions a corresponding function weight based on a corresponding quality of service level. The processing device also selects, for execution, a subset of the I/O operations, the subset comprising a number of I/O operations received at each function of the plurality of functions, wherein the number of I/O operations is determined according to the corresponding function weight of each function. The processing logic then executes the subset of I/O operations at the memory device.

公开(公告)号：US20210124498A1

公开(公告)日：2021-04-29

申请号：US16663031

申请日：2019-10-24

Applicant: Micron Technology, Inc.

Inventor： Luca Bert

IPC: G06F3/06 ,  G06F11/07 ,  G11C11/409

Abstract: A processing device in a memory system receives a request to execute a first operation of a first input/output (I/O) operation type at a memory device. The processing device further determines whether a second operation of a second I/O operation type is being executed at the memory device. Responsive to determining that the second operation is being executed, the processing device suspends the second operation after a delay time period, the delay time period corresponds to a first operation weight of the first operation and a second operation weight of the second operation, executes the first operation at the memory device, and responsive to determining that executing the first operation is complete, the processing device resumes execution of the second operation at the memory device.

公开(公告)号：US20250147682A1

公开(公告)日：2025-05-08

申请号：US19014020

申请日：2025-01-08

Applicant: Micron Technology, Inc.

Inventor： Luca Bert

IPC: G06F3/06

Abstract: A host system to query, during booting up of the host system, a superblock size in a connected memory sub-system. The host system can place write requests into separate streams and send the streams to the memory sub-system to store data of the write requests into separate sets of superblocks for the streams respectively. The host system can allocate, a plurality of log buffers for the streams respectively and record, into the log buffers, sequences of logical addresses as in the streams respectively. The host system can trim a stream, among the plurality of streams, by issuing commands to the memory sub-system to erase, according to the superblock size, an amount of data from a portion of a sequence of logical addresses recorded in a log buffer for the stream, causing the memory sub-system to free at least one superblock.

公开(公告)号：US12265717B2

公开(公告)日：2025-04-01

申请号：US18337819

申请日：2023-06-20

Applicant: Micron Technology, Inc.

Inventor： Luca Bert

IPC: G06F3/06

Abstract: A memory sub-system, such as a solid-state drive, configured to map a write stream to superblocks without the stream identifying a zone having a predetermined size in a namespace. The memory sub-system is configured to maintain, for the stream, a cursor configured to identify one of the plurality of superblocks as being reserved entirely for the stream; map, based on a superblock identified by the cursor, logical addresses of write commands in a contiguous segment of the stream to physical addresses in the superblock until the superblock is full; store data of write commands in the stream into based on mapping from logical addresses to physical addresses identified via the cursor; and allocate, for the cursor and in response to the superblock identified by the cursor being full, a free superblock available to continue mapping logical addresses to physical address.

公开(公告)号：US20250044946A1

公开(公告)日：2025-02-06

申请号：US18925594

申请日：2024-10-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luca Bert

IPC: G06F3/06 ,  G06F12/02

Abstract: An input/output (I/O) erase request directed at memory devices is received by a processing device. The erase request includes logical block address that is associated with a data object. The memory devices include groups of zones corresponding to sequential logical addresses. The plurality of zones are associated with a compound data object that includes a plurality of data objects, including the data object. One or more zones associated with the data object are identified. A data set counter associated with each of the one or more zones is decremented. The data set counter represents a number of sets of data associated with the zone. Responsive to determining that the data set counter associated with one of the one or more ones satisfies a criterion, the one of the one or more zones is a caused to be erased.

公开(公告)号：US20250021269A1

公开(公告)日：2025-01-16

申请号：US18770982

申请日：2024-07-12

Applicant: Micron Technology, Inc.

Inventor： Luca Bert ,  Sampath Ratnam

IPC: G06F3/06

Abstract: Various embodiments provide for performing a preconditioned operation on a memory system (e.g., the memory sub-system) based on queue identifiers of command requests received from a host system, where the precondition can include detection of command requests to be performed (e.g., executed) with respect to a sequence of memory addresses.

公开(公告)号：US20250021267A1

公开(公告)日：2025-01-16

申请号：US18770926

申请日：2024-07-12

Applicant: Micron Technology, Inc.

Inventor： Luca Bert ,  Sampath Ratnam

IPC: G06F3/06

Abstract: Various embodiments provide for block caching with queue identifiers on a memory system. In particular, when a write request to write host data is executed on a memory system that uses write/block caching and the host data is written to one or more cache blocks of a memory device of the memory system, the memory system can cause the queue identifier of the write request to be stored on the memory system in association with the host data. Subsequently, when the memory system moves (e.g., de-stages) data from one or more cache blocks (e.g., single-level cell (SLC) blocks) to one or more non-cache blocks (e.g., quad-level cell (QLC) blocks), the memory system can do so based on queue identifiers associated with host data written on one or more cache blocks of the memory system.

公开(公告)号：US12197976B2

公开(公告)日：2025-01-14

申请号：US18392457

申请日：2023-12-21

Applicant: Micron Technology, Inc.

Inventor： Luca Bert

IPC: G06F9/54 ,  G06F13/16

Abstract: A storage product having: a network interface operable on a computer network; a bus connector adapted to be connected to a computer bus; a storage device having a storage capacity accessible through network storage services provided over the network interface; and a processing device configured to at least generate storage access messages from incoming packets received by the network interface from the computer network. The storage product is operable in a standalone mode when no local host system is connected to the bus connector to control the storage product and operable in a slave mode when a local host system is connected to the bus connector to process a portion of the storage access messages.

公开(公告)号：US20240378098A1

公开(公告)日：2024-11-14

申请号：US18784807

申请日：2024-07-25

Applicant: Micron Technology, Inc.

Inventor： Luca Bert

IPC: G06F9/54 ,  G06F13/16

Abstract: A standalone storage product having: a first bus connector for connecting to an external processor; a second bus connector for connecting to an external network interface; a storage device accessible over the network interface; and a processing device configured to communicate, via the second bus connector, with the network interface to obtain storage access messages represented by incoming packets received at the network interface from a computer network. The processing device can: identify, from the storage access messages, first messages and second messages; provide, the first messages via the first bus connector, to the processor; and provide, the second messages, to the storage device without the second messages going through the processor. The storage device is configured to: receive, via the first bus connector, third messages from the processor; and execute commands in the second messages and the third messages to implement a network storage service.