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公开(公告)号:US4733110A
公开(公告)日:1988-03-22
申请号:US29194
申请日:1987-03-23
申请人: Hiroyuki Hara , Yasuhiro Sugimoto
发明人: Hiroyuki Hara , Yasuhiro Sugimoto
IPC分类号: H03K19/08 , H03K19/082 , H03K19/0944 , H03K19/01
CPC分类号: H03K19/09448
摘要: Logical NAND circuits, each consisting of a logical operational portion, an output control portion comprising the combination of a bipolar transistor and a plurality of NMOS transistors, and an output portion comprising first and second bipolar transistors connected in series between power supply voltage and the ground in which the merits of the MOS transistors and the bipolar transistors can be demonstrated by the particular combination of the two different kinds of the transistors in the logical circuit, thereby increasing the current driving performance while reducing power consumption without making the size of the logical circuit large.
摘要翻译: 逻辑NAND电路,每个由逻辑运算部分组成,输出控制部分包括双极晶体管和多个NMOS晶体管的组合,以及包括在电源电压和地之间串联连接的第一和第二双极晶体管的输出部分 其中可以通过逻辑电路中的两种不同种类的晶体管的特定组合来证明MOS晶体管和双极晶体管的优点,从而增加电流驱动性能,同时降低功耗而不使逻辑电路的尺寸 大。