公开(公告)号：US20140129164A1

公开(公告)日：2014-05-08

申请号：US14034553

申请日：2013-09-24

Applicant: Analog Devices Technology

Inventor： Jeremy R. Gorbold

IPC: G01R31/36

CPC classification number: G01R31/3835 ,  G01R31/396

Abstract: An example method to reduce data handling on lithium ion battery monitors is provided and includes receiving a request from a micro-controller for data associated with one or more cells, receiving signals corresponding to monitored properties from the cells, calculating derivative properties from the monitored properties, dividing a default data into a plurality of portions, and sending the derivative properties and one of the portions to the micro-controller according to at least a first compute logic option or a second compute logic option. The default data can include cell voltages, auxiliary inputs, stack voltage, reference output voltage, analog voltage output, analog voltage input, temperature, and reference buffer voltage. The default data is provided sequentially to the micro-controller in as many consecutive read backs as the number of portions, where each portion corresponds to the default data measured at a distinct time instant.

Abstract translation: 提供了一种减少锂离子电池监视器上的数据处理的示例性方法，包括从微控制器接收与一个或多个单元相关联的数据的请求，接收与来自单元的监视属性相对应的信号，从监视的属性计算导数特性 将默认数据分成多个部分，并且根据至少第一计算逻辑选项或第二计算逻辑选项将微分属性和部分之一发送到微控制器。 默认数据可以包括单元电压，辅助输入，堆栈电压，参考输出电压，模拟电压输出，模拟电压输入，温度和参考缓冲电压。 默认数据按照多个连续的回读顺序提供给微控制器，其中每个部分的数量对应于在不同时刻测量的默认数据。

公开(公告)号：US20140022007A1

公开(公告)日：2014-01-23

申请号：US13945978

申请日：2013-07-19

Applicant: Analog Devices Technology

Inventor： Linus Sheng ,  Christopher W. Mangelsdorf

IPC: G05F3/02

CPC classification number: G05F3/02 ,  H02M3/07 ,  H02M2003/075

Abstract: An apparatus for transferring charge has a first charge pump path with a plurality of stages having first capacitors, and a second charge pump path, also with a plurality of stage having second capacitors, in parallel with the first charge pump path. The first and second charge pump paths are coupled to share a common output node. The apparatus also has a timing circuit coupled with the first and second charge pump paths. Among other things, the timing circuit is configured to cause at least one of the first capacitors to periodically charge at least one of the second capacitors.

Abstract translation: 一种用于传送电荷的装置具有第一电荷泵路径，其具有多个阶段，该第一电荷泵路径具有第一电容器，第二电荷泵路径也具有与第一电荷泵路径并联的具有第二电容器的多个级。 第一和第二电荷泵路径被耦合以共享公共输出节点。 该装置还具有与第一和第二电荷泵路径耦合的定时电路。 其中，定时电路被配置为使得第一电容器中的至少一个周期性地对第二电容器中的至少一个充电。

公开(公告)号：US20130342551A1

公开(公告)日：2013-12-26

申请号：US13892531

申请日：2013-05-13

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Boris Lerner ,  Michael Meyer-Pundsack ,  Gopal Gudhur Karanam ,  Pradip Thaker

IPC: G06T1/60

CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T2200/28

Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.

公开(公告)号：US20130249923A1

公开(公告)日：2013-09-26

申请号：US13892508

申请日：2013-05-13

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Michael Meyer-Pundsack ,  Boris Lerner ,  Gopal Gudhur Karanam ,  Pradip Thacker

IPC: G06T1/60

CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T2200/28

Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of memory fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.

Abstract translation: 本发明的实施例提供了二维图像处理中的改进的定时控制，以便即使当处理操作转换到新的像素或新的像素帧时，仍然保持恒定的存储器读取速率和像素输出。 保持输入像素速率和输出像素速率之间的一对一关系，而不需要额外的时钟周期或存储器带宽，因为根据本发明的改进的定时控制通过预取一个新的像素数据列来利用空闲存储器带宽 在下一行或帧的第一像素块中，而当前行上的边缘像素块的新列被复制或清零。 当处理当前行上的边缘像素块时，下一行或帧的第一像素块中的数据就可以在没有额外的时钟周期或额外的存储器带宽的情况下进行计算。