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公开(公告)号：US08947446B2
公开(公告)日：2015-02-03
申请号：US13892531
申请日：2013-05-13
Applicant: Analog Devices Technology
Inventor： Boris Lerner , Michael Meyer-Pundsack , Gopal Gudhur Karanam , Pradip Thacker
CPC classification number: G06T1/20 , G06T1/60 , G06T2200/28
Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.
Abstract translation: 本发明的实施例提供了二维图像处理中的改进的定时控制，即使当处理操作转换到新的像素像素或一行像素时，仍然保持恒定的提取速率和像素输出。 保持输入像素速率和输出像素速率之间的一对一关系，而不需要额外的时钟周期或存储器带宽，因为根据本发明的改进的定时控制通过预取一个新的像素数据列来利用空闲存储器带宽 在下一行或帧的第一像素块中，而当前行上的边缘像素块的新列被复制或清零。 当处理当前行上的边缘像素块时，下一行或帧的第一像素块中的数据就可以在没有额外的时钟周期或额外的存储器带宽的情况下进行计算。
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公开(公告)号：US08766992B2
公开(公告)日：2014-07-01
申请号：US13892508
申请日：2013-05-13
Applicant: Analog Devices Technology
Inventor： Boris Lerner , Michael Meyer-Pundsack , Gopal Gudhur Karanam , Pradip Thaker
CPC classification number: G06T1/20 , G06T1/60 , G06T2200/28
Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of memory fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.
Abstract translation: 本发明的实施例提供了二维图像处理中的改进的定时控制，以便即使当处理操作转换到新的像素或新的像素帧时，仍然保持恒定的存储器读取速率和像素输出。 保持输入像素速率和输出像素速率之间的一对一关系，而不需要额外的时钟周期或存储器带宽，因为根据本发明的改进的定时控制通过预取一个新的像素数据列来利用空闲存储器带宽 在下一行或帧的第一像素块中，而当前行上的边缘像素块的新列被复制或清零。 当处理当前行上的边缘像素块时，下一行或帧的第一像素块中的数据就可以在没有额外的时钟周期或额外的存储器带宽的情况下进行计算。
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公开(公告)号：US20130342551A1
公开(公告)日：2013-12-26
申请号：US13892531
申请日：2013-05-13
Applicant: ANALOG DEVICES TECHNOLOGY
Inventor： Boris Lerner , Michael Meyer-Pundsack , Gopal Gudhur Karanam , Pradip Thaker
IPC: G06T1/60
CPC classification number: G06T1/20 , G06T1/60 , G06T2200/28
Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.
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公开(公告)号：US20130249923A1
公开(公告)日：2013-09-26
申请号：US13892508
申请日：2013-05-13
Applicant: ANALOG DEVICES TECHNOLOGY
Inventor： Michael Meyer-Pundsack , Boris Lerner , Gopal Gudhur Karanam , Pradip Thacker
IPC: G06T1/60
CPC classification number: G06T1/20 , G06T1/60 , G06T2200/28
Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of memory fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.
Abstract translation: 本发明的实施例提供了二维图像处理中的改进的定时控制，以便即使当处理操作转换到新的像素或新的像素帧时，仍然保持恒定的存储器读取速率和像素输出。 保持输入像素速率和输出像素速率之间的一对一关系，而不需要额外的时钟周期或存储器带宽，因为根据本发明的改进的定时控制通过预取一个新的像素数据列来利用空闲存储器带宽 在下一行或帧的第一像素块中，而当前行上的边缘像素块的新列被复制或清零。 当处理当前行上的边缘像素块时，下一行或帧的第一像素块中的数据就可以在没有额外的时钟周期或额外的存储器带宽的情况下进行计算。
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