公开(公告)号：US20200151058A1

公开(公告)日：2020-05-14

申请号：US16746786

申请日：2020-01-17

Applicant: Micron Technology, Inc.

Inventor： Mustafa N. Kaynak ,  Larry J. Koudele ,  Michael Sheperek ,  Patrick R. Khayat ,  Sampath K. Ratnam

IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52

Abstract: A first data stored at a first portion of a memory cell and a second data stored at a second portion of the memory cell are identified. A first error rate associated with first data stored at the first portion of the memory cell is determined. The first error rate is adjusted to exceed a second error rate associated with the second data stored at the second portion of the memory cell. A determination is made as to whether the first error rate exceeds a threshold. The second data stored at the second portion of the memory cell is provided for use in an error correction operation by a controller associated with the memory cell in response to determining that the first error rate exceeds the threshold.

公开(公告)号：US20200082887A1

公开(公告)日：2020-03-12

申请号：US16128905

申请日：2018-09-12

Applicant: Micron Technology, Inc.

Inventor： Gerald L. Cadloni ,  Michael Sheperek

IPC: G11C16/16 ,  G11C8/06 ,  G06F12/02

Abstract: A memory component includes a memory configured to store an updatable trim profile that is user-modifiable. The updatable trim profile includes address information corresponding to a trim register to be modified, command information corresponding to an action to be performed, and data corresponding to the action to be performed. A processing device that is coupled to the memory component is configured to receive an instruction to modify the trim register, read contents of the updatable trim profile, and modify the trim register based on the address information, the action to be performed on the trim register, and the data.

公开(公告)号：US10540228B2

公开(公告)日：2020-01-21

申请号：US15914402

申请日：2018-03-07

Applicant: Micron Technology, Inc.

Inventor： Mustafa N. Kaynak ,  Larry J. Koudele ,  Michael Sheperek ,  Patrick R Khayat ,  Sampath K Ratnam

IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52

Abstract: A first data stored at a first portion of a memory cell and a second data stored at a second portion of the memory cell are identified. A first error rate associated with first data stored at the first portion of the memory cell is determined. The first error rate is adjusted to exceed a second error rate associated with the second data stored at the second portion of the memory cell. A determination is made as to whether the first error rate exceeds a threshold. The second data stored at the second portion of the memory cell is provided for use in an error correction operation in response to determining that the first error rate exceeds the threshold.