公开(公告)号：US20060240624A1

公开(公告)日：2006-10-26

申请号：US11472941

申请日：2006-06-22

Applicant: Chih-Mu Huang ,  Mingchu King ,  Yun Chang

Inventor： Chih-Mu Huang ,  Mingchu King ,  Yun Chang

IPC: H01L21/336

CPC classification number: H01L27/10805 ,  H01L27/10888

Abstract: A single transistor planar RAM memory cell with improved charge retention and a method for forming the same, the method including providing forming a pass transistor structure adjacent a storage capacitor structure separated by a predetermined distance; carrying out a first ion implantation process to form first and second doped regions adjacent either side of the pass transistor structure, the first doped region defined by the predetermined distance; depositing a spacer dielectric layer; etching back the spacer dielectric layer to leave an unetched spacer dielectric layer portion overlying the first doped region while forming a sidewall spacer of a predetermined width overlying a first portion of the second doped region; and, carrying out a second ion implantation process to form a relatively higher dopant concentration in a second portion of the second doped region.

公开(公告)号：US06392285B1

公开(公告)日：2002-05-21

申请号：US09461014

申请日：1999-12-14

Applicant: Chih-Mu Huang ,  Chuan-Jane Chao ,  Chi-Hung Kao

Inventor： Chih-Mu Huang ,  Chuan-Jane Chao ,  Chi-Hung Kao

IPC: H01L27082

CPC classification number: H01L28/40 ,  H01L27/0635

Abstract: The present invention discloses a simple and convenient method for fabricating a capacitor device with BiCMOS processes. An electrode of the capacitor device formed according to the present invention is an ion doping region formed in an epitaxy layer so that the thickness of the dielectric layer of the capacitor device decreased relative to a specific ion concentration. Accordingly, the capacitor device formed therein has a high capacitance and good performance.

Abstract translation: 本发明公开了一种用于制造具有BiCMOS工艺的电容器器件的简单方便的方法。 根据本发明形成的电容器装置的电极是形成在外延层中的离子掺杂区域，使得电容器装置的电介质层的厚度相对于特定离子浓度降低。 因此，其中形成的电容器器件具有高电容和良好的性能。

公开(公告)号：US06200859B1

公开(公告)日：2001-03-13

申请号：US09454419

申请日：1999-12-03

Applicant: Chih-Mu Huang ,  Jung-Yu Tsai ,  Shing-Hwa Renn ,  Shu-Huei Lin

Inventor： Chih-Mu Huang ,  Jung-Yu Tsai ,  Shing-Hwa Renn ,  Shu-Huei Lin

IPC: H01L21336

CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

Abstract: A split-gate flash memory is formed by a method described in the following steps. A tunnelling oxide layer, a first conductive layer, and a hard mask layer are formed on a substrate in sequence. A drain opening and a floating gate opening are formed on the hard mask layer by defining the hard mask layer in order to expose the first conductive layer. A first polyoxide layer and a second polyoxide layer are formed on the first conductive layer exposed by the drain opening and the floating gate opening, respectively. The first polyoxide layer and the first conductive layer beneath the first polyoxide layer are removed to expose the substrate in the drain opening. A drain region is formed in the substrate in the drain opening. The hard mask layer is removed, and the first conductive layer is etched into a floating gate using the second polyoxide layer as a mask. A split-gate oxide layer and a second conductive layer are formed on the resulting structure in sequence. A control gate is formed by defining the second conductive layer, and a source region beside the floating gate is formed in the substrate.

Abstract translation: 通过以下步骤中描述的方法形成分路闸闪存。 在衬底上依次形成隧穿氧化物层，第一导电层和硬掩模层。 通过限定硬掩模层以在第一导电层上露出，在硬掩模层上形成漏极开口和浮动开口。 分别在由排水开口和浮动开口露出的第一导电层上形成第一多氧化物层和第二多氧化物层。 去除第一多氧化物层和第一多氧化物层下面的第一导电层以露出排水开口中的衬底。 漏极区域形成在排水开口中的衬底中。 去除硬掩模层，并且使用第二聚氧化物层作为掩模将第一导电层蚀刻到浮动栅极中。 在所得结构上依次形成分裂栅氧化层和第二导电层。 通过限定第二导电层形成控制栅极，并且在衬底中形成浮置栅极旁边的源极区域。