公开(公告)号：US20240363765A1

公开(公告)日：2024-10-31

申请号：US18306488

申请日：2023-04-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Gerben Doornbos ,  Georgios Vellianitis ,  Marcus Johannes Henricus Van Dal ,  Yu-Ming Lin ,  Oreste Madia

IPC分类号： H01L29/788 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L29/7883 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/66825

摘要： Some embodiments relate to an integrated device, including a control gate over a substrate, the control gate having a first length; a tunnel dielectric on the control gate; a floating gate having a second length on the tunnel dielectric, the tunnel dielectric separating the control gate and the floating gate; a blocking dielectric on the floating gate; a channel on the blocking dielectric, the blocking dielectric separating the channel and the floating gate; and source/drain terminals on the channel, wherein the first length of the control gate is less than the second length of the floating gate.

公开(公告)号：US20240349499A1

公开(公告)日：2024-10-17

申请号：US18342713

申请日：2023-06-27

申请人： Winbond Electronics Corp.

发明人： Tzu-Yun Huang ,  Chung-Hsien Liu

IPC分类号： H10B41/35 ,  H01L29/423 ,  H10B41/10

CPC分类号： H10B41/35 ,  H01L29/42324 ,  H10B41/10

摘要： A memory device and a manufacturing method thereof are provided. The memory device includes: active regions, defined in a semiconductor substrate; word line structures, formed on the semiconductor substrate, and intersected with the active regions, wherein each of the word line structures includes a floating gate and a control gate stacked on the floating gate; first protection layers, respectively covering an upper part of the control gate in one of the word line structures, wherein a bottom end of the control gate in each word line structure is lower than a bottom end of each first protection layer; and a second protection layer, covering the first protection layers, and wrapping the word line structures.

公开(公告)号：US12113135B2

公开(公告)日：2024-10-08

申请号：US18174687

申请日：2023-02-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Chu Lin ,  Wen-Chih Chiang ,  Chi-Chung Jen ,  Ming-Hong Su ,  Mei-Chen Su ,  Chia-Wei Lee ,  Kuan-Wei Su ,  Chia-Ming Pan

IPC分类号： H01L29/788 ,  H01L29/06 ,  H01L29/423 ,  H10B41/00

CPC分类号： H01L29/788 ,  H01L29/0649 ,  H01L29/42324 ,  H10B41/00

摘要： Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first terminal coupled to a substrate of the semiconductor structure. The first terminal comprises a tunneling layer formed on the substrate, a first conductive structure formed on the tunneling layer, and a dielectric structure formed on a top surface and on a first curved side surface of the first conductive structure. The semiconductor structure includes a second terminal coupled to the substrate. The second terminal comprises a second conductive structure formed on an isolation structure. The second conductive structure has a second curved side surface, and the dielectric structure is disposed between the first curved side surface and the second curved side surface.

公开(公告)号：US12096623B2

公开(公告)日：2024-09-17

申请号：US17309775

申请日：2019-04-09

申请人： Institute of Microelectronics, Chinese Academy of Sciences

发明人： Huilong Zhu ,  Weixing Huang ,  Kunpeng Jia

IPC分类号： H10B41/27 ,  H01L29/423 ,  H01L29/788

CPC分类号： H10B41/27 ,  H01L29/42324 ,  H01L29/788

摘要： Disclosed are a semiconductor device, a method for manufacturing the same, an integrated circuit, and an electronic apparatus. The semiconductor device includes: a substrate; an active region on the substrate, the active region includes a first source and drain layer, a channel layer, and a second source and drain layer sequentially stacked on the substrate; a gate stack formed around an outer periphery of the channel layer; and an intermediate dielectric layer and a second conductive layer around an outer periphery of the gate stack and an outer periphery of the active region. The device and method provided by the present disclosure are used to solve the technical problem that the performances of the vertical device in the related art need to be improved. A semiconductor device with better performances is provided.

公开(公告)号：US12079415B2

公开(公告)日：2024-09-03

申请号：US17963125

申请日：2022-10-10

申请人： Micron Technology, Inc.

发明人： Pankaj Sharma

IPC分类号： G06F3/041 ,  G06F3/01 ,  G06F3/0481 ,  G06F3/04817 ,  G06F3/0482 ,  G06F3/0484 ,  G06F3/04883 ,  G06F3/04886 ,  G06Q10/10 ,  G11B27/10 ,  H01L29/24 ,  H01L29/423 ,  H01L29/78 ,  H01L29/788 ,  H04L65/403 ,  H04N21/00 ,  H04N21/472 ,  H04N21/84 ,  H04N21/854

CPC分类号： G06F3/0416 ,  G06F3/0481 ,  G06F3/04817 ,  G06F3/0482 ,  G06F3/0484 ,  G06F3/04883 ,  G06F3/04886 ,  G06Q10/10 ,  H01L29/24 ,  H01L29/42324 ,  H01L29/7827 ,  H01L29/78391 ,  H01L29/7889 ,  H04L65/403 ,  H04N21/47205 ,  H04N21/854 ,  G06F3/01 ,  G06F2203/04105 ,  G06F2203/04803 ,  G06F2203/04808 ,  G11B27/10 ,  H04N21/00 ,  H04N21/84

摘要： Some embodiments include a ferroelectric transistor having an active region which includes a first source/drain region, a second source/drain region vertically offset from the first source/drain region, and a channel region between the first and second source/drain regions. A first conductive gate is operatively adjacent to the channel region of the active region. Insulative material is between the first conductive gate and the channel region. A second conductive gate is adjacent to the first conductive gate. Ferroelectric material is between the first and second conductive gates. Some embodiments include integrated memory. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US12075623B2

公开(公告)日：2024-08-27

申请号：US18186062

申请日：2023-03-17

申请人： SK hynix Inc.

发明人： Changhan Kim ,  In Ku Kang ,  Sun Young Kim

IPC分类号： H10B43/27 ,  H01L21/28 ,  H01L29/423 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35 ,  H10B63/00 ,  H10N70/00 ,  H10N70/20

CPC分类号： H10B43/27 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/4234 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35 ,  H10B63/845 ,  H10N70/066 ,  H10N70/231

摘要： A semiconductor device includes a stacked structure with insulating layers and conductive layers that are alternately stacked on each other, a hard mask pattern on the stacked structure, a channel structure penetrating the hard mask pattern and the stacked structure, insulating patterns interposed between the insulating layers and the channel structure, wherein the insulating patterns protrude farther towards the channel structure than a sidewall of the hard mask pattern, and a memory layer interposed between the stacked structure and the channel structure, wherein the memory layer fills a space between the insulating patterns.

公开(公告)号：US20240282369A1

公开(公告)日：2024-08-22

申请号：US18645184

申请日：2024-04-24

申请人： Silicon Storage Technology, Inc.

发明人： Hieu Van Tran ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

IPC分类号： G11C11/54 ,  G06N3/045 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  H01L29/423 ,  H01L29/788 ,  H10B41/30

CPC分类号： G11C11/54 ,  G06N3/045 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/7883 ,  H10B41/30

摘要： A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region disposed between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell rows, and fourth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the fourth lines, and provide a first plurality of outputs as electrical currents on the third lines.

公开(公告)号：US20240276723A1

公开(公告)日：2024-08-15

申请号：US18463500

申请日：2023-09-08

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： SUNGBOK LEE ,  JUNHEE LIM

IPC分类号： H10B43/27 ,  H01L29/423 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

CPC分类号： H10B43/27 ,  H01L29/42324 ,  H01L29/4234 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

摘要： A vertical memory device includes a memory channel structure disposed on a substrate, a plurality of division layers disposed on the substrate and a gate electrode structure. The memory channel structure extends in a vertical direction substantially perpendicular to an upper surface of the substrate. The division layers contact the memory channel structure, respectively. The gate electrode structure contacts a sidewall of the memory channel structure, which may include a filling pattern, a channel disposed on a sidewall of the filling pattern and a charge storage structure disposed on an outer sidewall of the channel and sidewalls of the division layers, each of which extends through a portion of the charge storage structure and a portion of the channel. Each of the charge storage structure and the channel is divided into two parts by the division layers.

公开(公告)号：US12052861B2

公开(公告)日：2024-07-30

申请号：US18321487

申请日：2023-05-22

申请人： STMicroelectronics (Rousset) SAS

发明人： François Tailliet

IPC分类号： H01L21/00 ,  G11C7/18 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H10B41/00 ,  H10B41/35 ,  H01L29/788

CPC分类号： H10B41/00 ,  G11C7/18 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66825 ,  H10B41/35 ,  H01L29/7881

摘要： An EEPROM memory integrated circuit includes memory cells arranged in a memory plane. Each memory cell includes an access transistor in series with a state transistor. Each access transistor is coupled, via its source region, to the corresponding source line and each state transistor is coupled, via its drain region, to the corresponding bit line. The floating gate of each state transistor rests on a dielectric layer having a first part with a first thickness, and a second part with a second thickness that is less than the first thickness. The second part is located on the source side of the state transistor.

公开(公告)号：US20240250168A1

公开(公告)日：2024-07-25

申请号：US18311102

申请日：2023-05-02

申请人： DB HiTek Co., Ltd.

发明人： Jong Min KIM ,  Geum Ho AHN

IPC分类号： H01L29/78 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L29/7816 ,  H01L29/404 ,  H01L29/42324 ,  H01L29/66681

摘要： Disclosed is a high voltage semiconductor device and a method of manufacturing the same and, more particularly, a high voltage semiconductor device and a method of manufacturing the same enabling more effective integration through improvement of breakdown voltage (BV) characteristics during device turn-on and/or turn-off and consequent improvement of specific on-resistance (Rsp) characteristics by forming or including a floating gate and/or a connection structure on a substrate, between a gate electrode and a drain.