公开(公告)号：US08498342B1

公开(公告)日：2013-07-30

申请号：US12511629

申请日：2009-07-29

Applicant: Li Sha ,  Ching-Han Tsai ,  Chi-Kuang Chen ,  Yaojun Luo ,  Guan-Ming Su ,  Ye Zhou

Inventor： Li Sha ,  Ching-Han Tsai ,  Chi-Kuang Chen ,  Yaojun Luo ,  Guan-Ming Su ,  Ye Zhou

IPC: H04N11/02

CPC classification number: H04N19/44 ,  H04N19/423 ,  H04N19/43 ,  H04N19/86

Abstract: This disclosure describes tools capable of generating messages for use in deblocking filtering a video stream, the messages based on prediction parameters extracted from the video stream.

Abstract translation: 本公开描述了能够生成用于去视频流过滤的消息的工具，该消息基于从视频流中提取的预测参数。

公开(公告)号：US20100095307A1

公开(公告)日：2010-04-15

申请号：US12575446

申请日：2009-10-07

Applicant: Lincheng WANG ,  Ching-Han TSAI ,  Cheng-Lun CHANG ,  UMA Shankar DURVASULA ,  Jau-Wen REN

Inventor： Lincheng WANG ,  Ching-Han TSAI ,  Cheng-Lun CHANG ,  UMA Shankar DURVASULA ,  Jau-Wen REN

IPC: G06F3/00 ,  G06F9/46

CPC classification number: G06F13/4234 ,  G06F2213/0038 ,  H04N21/443

Abstract: A forced lock-step operation between a CPU (software) and the hardware is eliminated by unburdening the CPU from monitoring the hardware until it is finished with its task. This is done by providing a data/control message queue into which the CPU writes combined data/control messages and places an End tag into the queue when finished. The hardware checks the content of the message queue and starts decoding the incoming data. The hardware processes the data read from the message queue and the processed data is then written back into the message queue for use by the software. The hardware raises an interrupt signal to the CPU when reaching the End tag. Speed differences between hardware and software can be compensated for by changing the depth of the queue.

Abstract translation: CPU（软件）和硬件之间的强制锁定步骤操作通过卸载CPU来监视硬件直到完成任务来消除。 这通过提供一个数据/控制消息队列来完成，CPU写入组合的数据/控制消息，并在结束时将一个End标签放入队列。 硬件检查消息队列的内容，并开始对传入的数据进行解码。 硬件处理从消息队列读取的数据，然后处理的数据被写回到消息队列中供软件使用。 当达到End标签时，硬件会向CPU提供中断信号给CPU。 可以通过改变队列的深度来补偿硬件和软件之间的速度差异。

公开(公告)号：US08327046B1

公开(公告)日：2012-12-04

申请号：US13396981

申请日：2012-02-15

Applicant: Li Sha ,  Ching-Han Tsai ,  Chengjun Wang

Inventor： Li Sha ,  Ching-Han Tsai ,  Chengjun Wang

IPC: G06F3/00

CPC classification number: H04N19/433 ,  G06F5/065 ,  H04N19/426 ,  H04N19/44

Abstract: In one embodiment the present invention includes an apparatus having a random access memory, a first interface, and a second interface. The first interface is coupled between the random access memory and a plurality of storage devices, and operates in a first in first out (FIFO) manner. The second interface is coupled between the random access memory and a processor, and operates in a random access manner. As a result, the processor is not required to be in the loop when data is being transferred between the random access memory and the storage devices.

Abstract translation: 在一个实施例中，本发明包括具有随机存取存储器，第一接口和第二接口的装置。 第一接口耦合在随机存取存储器和多个存储设备之间，并且以先进先出（FIFO）的方式操作。 第二接口耦合在随机存取存储器和处理器之间，并以随机存取方式操作。 结果，当在随机存取存储器和存储设备之间传送数据时，处理器不需要处于循环中。

公开(公告)号：US08275978B1

公开(公告)日：2012-09-25

申请号：US12504080

申请日：2009-07-16

Applicant: Li Sha ,  Ching-Han Tsai ,  Chi-Kuang Chen ,  Tzun-Wei Lee

Inventor： Li Sha ,  Ching-Han Tsai ,  Chi-Kuang Chen ,  Tzun-Wei Lee

IPC: G06F9/38

CPC classification number: G06F9/30058 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/322 ,  G06F9/324 ,  G06F9/3806

Abstract: In one embodiment the present invention includes a microprocessor that has a pipeline circuit, a branch circuit, and a control circuit. The pipeline circuit pipelines instructions for the microprocessor. The branch circuit is coupled to the pipeline circuit and operates to store branch information. The control circuit is coupled to the pipeline circuit and the branch circuit. The control circuit stores a first branch information from the pipeline circuit to the branch circuit when a first condition is met. The control circuit retrieves a second branch information from the branch stack circuit to the pipeline circuit when a second condition is met. In this manner, the need for dedicated pipeline flush circuitry is avoided.

Abstract translation: 在一个实施例中，本发明包括具有流水线电路，分支电路和控制电路的微处理器。 管道电路管道指令为微处理器。 分支电路耦合到流水线电路并操作以存储分支信息。 控制电路耦合到流水线电路和分支电路。 当满足第一条件时，控制电路将来自流水线电路的第一分支信息存储到分支电路。 当满足第二条件时，控制电路从分支堆栈电路检索第二分支信息到流水线电路。 以这种方式，避免了专用管道冲洗电路的需要。

公开(公告)号：US07982641B1

公开(公告)日：2011-07-19

申请号：US12613830

申请日：2009-11-06

Applicant: Guan-Ming Su ,  Leung Chung Lai ,  Wenchi Hsu ,  Qian Tang ,  Li Sha ,  Ching-Han Tsai

Inventor： Guan-Ming Su ,  Leung Chung Lai ,  Wenchi Hsu ,  Qian Tang ,  Li Sha ,  Ching-Han Tsai

IPC: H03M7/00

CPC classification number: H03M7/4006 ,  H04N19/13 ,  H04N19/61

Abstract: A system including a binarization module, an encoding module, and a prediction module. The binarization module is configured to binarize a syntax element and to generate symbols. The encoding module is configured to encode the symbols using context-adaptive binary arithmetic coding (CABAC). The prediction module is configured to generate a prediction for a number of renormalizations to be performed to renormalize an interval range when encoding one of the symbols. The encoding module encodes a next symbol following the one of the symbols based on the prediction before renormalization of the interval range is actually completed.

Abstract translation: 一种包括二值化模块，编码模块和预测模块的系统。 二值化模块被配置为二进制化语法元素并生成符号。 编码模块被配置为使用上下文自适应二进制算术编码（CABAC）对符号进行编码。 预测模块被配置为生成对要执行的多个重新归一化的预测，以便在对符号之一进行编码时对间隔范围进行重新归一化。 编码模块基于在实际完成间隔范围的重新归一化之前的预测，对符号之一之后的下一个符号进行编码。

公开(公告)号：US08477146B2

公开(公告)日：2013-07-02

申请号：US12511238

申请日：2009-07-29

Applicant: Shuhua Xiang ,  Li Sha ,  Ching-Han Tsai

Inventor： Shuhua Xiang ,  Li Sha ,  Ching-Han Tsai

IPC: G06T9/00 ,  G06F12/02 ,  G06F12/10

CPC classification number: H04N19/423 ,  H04N19/433 ,  H04N19/44 ,  H04N19/61

Abstract: Devices, methods, and other embodiments associated with processing rasterized data are described. In one embodiment, an apparatus includes translation logic for converting lines of rasterized pixel data of a compressed image to a plurality of two-dimensional data blocks. The lines of rasterized pixel data are stored in consecutive memory locations. Each data block is stored in a consecutive memory location. The apparatus includes decompression logic for at least partially decompressing the compressed image based, at least in part, on the two-dimensional data blocks.

公开(公告)号：US07707334B2

公开(公告)日：2010-04-27

申请号：US11282531

申请日：2005-11-18

Applicant: Lincheng Wang ,  Ching-Han Tsai ,  Cheng-Lun Chang ,  Uma Shankar Durvasula ,  Jau-Wen Ren

Inventor： Lincheng Wang ,  Ching-Han Tsai ,  Cheng-Lun Chang ,  Uma Shankar Durvasula ,  Jau-Wen Ren

IPC: G06F3/00 ,  G06F5/00

CPC classification number: G06F13/4234 ,  G06F2213/0038 ,  H04N21/443

Abstract: A forced lock-step operation between a CPU (software) and the hardware is eliminated by unburdening the CPU from monitoring the hardware until it is finished with its task. This is done by providing a data/control message queue into which the CPU writes combined data/control messages and places an End tag into the queue when finished. The hardware checks the content of the message queue and starts decoding the incoming data. The hardware processes the data read from the message queue and the processed data is then written back into the message queue for use by the software. The hardware raises an interrupt signal to the CPU when reaching the End tag. Speed differences between hardware and software can be compensated for by changing the depth of the queue.

Abstract translation: CPU（软件）和硬件之间的强制锁定步骤操作通过卸载CPU来监视硬件直到完成任务来消除。 这通过提供一个数据/控制消息队列来完成，CPU写入组合的数据/控制消息，并在结束时将一个End标签放入队列。 硬件检查消息队列的内容，并开始对传入的数据进行解码。 硬件处理从消息队列读取的数据，然后处理的数据被写回到消息队列中供软件使用。 当达到End标签时，硬件会向CPU提供中断信号给CPU。 可以通过改变队列的深度来补偿硬件和软件之间的速度差异。

公开(公告)号：US20070130394A1

公开(公告)日：2007-06-07

申请号：US11282531

申请日：2005-11-18

Applicant: Lincheng Wang ,  Ching-Han Tsai ,  Cheng-Lun Chang ,  Uma Durvasula ,  Jau-Wen Ren

Inventor： Lincheng Wang ,  Ching-Han Tsai ,  Cheng-Lun Chang ,  Uma Durvasula ,  Jau-Wen Ren

IPC: G06F5/00

CPC classification number: G06F13/4234 ,  G06F2213/0038 ,  H04N21/443

Abstract: A forced lock-step operation between a CPU (software) and the hardware is eliminated by unburdening the CPU from monitoring the hardware until it is finished with its task. This is done by providing a data/control message queue into which the CPU writes combined data/control messages and places an End tag into the queue when finished. The hardware checks the content of the message queue and starts decoding the incoming data. The hardware processes the data read from the message queue and the processed data is then written back into the message queue for use by the software. The hardware raises an interrupt signal to the CPU when reaching the End tag. Speed differences between hardware and software can be compensated for by changing the depth of the queue.

Abstract translation: CPU（软件）和硬件之间的强制锁定步骤操作通过卸载CPU来监视硬件直到完成任务来消除。 这通过提供一个数据/控制消息队列来完成，CPU写入组合的数据/控制消息，并在结束时将一个End标签放入队列。 硬件检查消息队列的内容，并开始对传入的数据进行解码。 硬件处理从消息队列读取的数据，然后处理的数据被写回到消息队列中供软件使用。 当达到End标签时，硬件会向CPU提供中断信号给CPU。 可以通过改变队列的深度来补偿硬件和软件之间的速度差异。