公开(公告)号：US08878870B1

公开(公告)日：2014-11-04

申请号：US12533554

申请日：2009-07-31

Applicant: Satish Kumar Vutukuri ,  Haohong Wang ,  Li Sha ,  Tao Xie ,  Ching-Han Tsai ,  Tzun-Wei Lee ,  Leung Chung Lai ,  Shuhua Xiang

Inventor： Satish Kumar Vutukuri ,  Haohong Wang ,  Li Sha ,  Tao Xie ,  Ching-Han Tsai ,  Tzun-Wei Lee ,  Leung Chung Lai ,  Shuhua Xiang

IPC: G09G5/00 ,  G09G5/377 ,  G06T3/40 ,  G06T15/00 ,  G06T15/40 ,  G06T15/50

CPC classification number: G09G5/377 ,  G06F3/14 ,  G09G5/14 ,  G09G2310/0229 ,  G09G2340/125 ,  G09G2350/00

Abstract: Embodiments of the present invention provide graphic processing techniques and configurations including an apparatus comprising a storage medium having stored therein a table comprising information about respective positions and sizes of a number of rectangular blocks, the rectangular blocks to substantially form at least one plane having an arbitrary shape object, and at least one overlay engine operatively coupled with the table and associated with the at least one plane to request the information about the respective positions and the sizes of the number of rectangular blocks to provide graphics overlay of the arbitrary shape object. Other embodiments may be described and/or claimed.

Abstract translation: 本发明的实施例提供了图形处理技术和配置，其包括包括存储介质的设备，其中存储有包括关于多个矩形块的相应位置和大小的信息的表格，矩形块基本上形成至少一个具有任意 以及至少一个覆盖引擎，其可操作地与所述工作台耦合并与所述至少一个平面相关联，以请求关于矩形块的数量的相应位置和尺寸的信息以提供所述任意形状对象的图形叠加。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20100325334A1

公开(公告)日：2010-12-23

申请号：US12819451

申请日：2010-06-21

Applicant: Ching-Han TSAI ,  Cheng-Lun Chang ,  Jung-Tao Liu ,  Ya-Chau Yang

Inventor： Ching-Han TSAI ,  Cheng-Lun Chang ,  Jung-Tao Liu ,  Ya-Chau Yang

IPC: G06F13/28

CPC classification number: G06F15/163 ,  G06F15/17

Abstract: An external memory based FIFO (xFIFO) apparatus coupled to an external memory and a register bus is disclosed. The xFIFO apparatus includes an xFIFO engine, a wDMA engine, an rDMA engine, a first virtual FIFO, and a second virtual FIFO. The xFIFO engine receives a FIFO command from the register bus and generates a writing DMA command and a reading DMA command. The wDMA engine receives the writing DMA command from the xFIFO engine and forwards an incoming data to the external memory. The rDMA engine receives the reading DMA command from the xFIFO engine and pre-fetches a FIFO data from the external memory. The wDMA engine and the rDMA engine synchronize with each other via the first virtual FIFO and the second virtual FIFO.

Abstract translation: 公开了一种耦合到外部存储器和寄存器总线的基于外部存储器的FIFO（xFIFO）装置。 xFIFO装置包括xFIFO引擎，wDMA引擎，rDMA引擎，第一虚拟FIFO和第二虚拟FIFO。 xFIFO引擎从寄存器总线接收FIFO命令，并产生写入DMA命令和读取DMA命令。 wDMA引擎从xFIFO引擎接收写入DMA命令，并将传入的数据转发到外部存储器。 rDMA引擎从xFIFO引擎接收读取DMA命令，并从外部存储器中预取FIFO数据。 wDMA引擎和rDMA引擎通过第一虚拟FIFO和第二虚拟FIFO相互同步。

公开(公告)号：US20100026697A1

公开(公告)日：2010-02-04

申请号：US12511238

申请日：2009-07-29

Applicant: Shuhua XIANG ,  Li SHA ,  Ching-Han TSAI

Inventor： Shuhua XIANG ,  Li SHA ,  Ching-Han TSAI

IPC: G06F12/00

CPC classification number: H04N19/423 ,  H04N19/433 ,  H04N19/44 ,  H04N19/61

Abstract: Devices, methods, and other embodiments associated with processing rasterized data are described. In one embodiment, an apparatus includes translation logic for converting lines of rasterized pixel data of a compressed image to a plurality of two-dimensional data blocks. The lines of rasterized pixel data are stored in consecutive memory locations. Each data block is stored in a consecutive memory location. The apparatus includes decompression logic for at least partially decompressing the compressed image based, at least in part, on the two-dimensional data blocks.

Abstract translation: 描述了与处理光栅化数据相关联的设备，方法和其他实施例。 在一个实施例中，一种装置包括用于将压缩图像的光栅化像素数据的线转换成多个二维数据块的转换逻辑。 光栅化像素数据的行存储在连续的存储单元中。 每个数据块被存储在连续的存储单元中。 该装置包括用于至少部分地基于二维数据块至少部分地解压缩压缩图像的解压缩逻辑。

公开(公告)号：US08711019B1

公开(公告)日：2014-04-29

申请号：US13185354

申请日：2011-07-18

Applicant: Guan-Ming Su ,  Leung Chung Lai ,  Wenchi Hsu ,  Qian Tang ,  Li Sha ,  Ching-Han Tsai

Inventor： Guan-Ming Su ,  Leung Chung Lai ,  Wenchi Hsu ,  Qian Tang ,  Li Sha ,  Ching-Han Tsai

IPC: H03M7/00

CPC classification number: H03M7/4006 ,  H04N19/13 ,  H04N19/61

Abstract: A system including a binarization module, a prediction module, and a shifting module. The encoding module is configured to encode symbols using context-adaptive binary arithmetic coding, in which the symbols are generated by binarizing a syntax element. The prediction module is configured to generate a prediction for a number of renormalizations to be performed to renormalize an interval range when encoding one of the symbols. The shifting module is configured to generate a renormalized interval range by shifting the binarized syntax element R times, where R is a number of leading zeros before a 1 in the binarized syntax element. The encoding module is configured to encode a next symbol following the one of the symbols based on the renormalized interval range.

Abstract translation: 一种包括二值化模块，预测模块和移位模块的系统。 编码模块被配置为使用上下文自适应二进制算术编码对符号进行编码，其中通过二元化语法元素来生成符号。 预测模块被配置为生成对要执行的多个重新归一化的预测，以便在对符号之一进行编码时对间隔范围进行重新归一化。 移位模块被配置为通过移位二进制化的语法元素R times来生成重新归一化的间隔范围，其中R是二进制化语法元素中的1之前的前导零的数量。 编码模块被配置为基于重新归一化的间隔范围对符号之后的下一个符号进行编码。

公开(公告)号：US08494059B1

公开(公告)日：2013-07-23

申请号：US12511425

申请日：2009-07-29

Applicant: Hongjie Guan ,  Junqiang Lan ,  Yaojun Luo ,  Guan-Ming Su ,  Ching-Han Tsai ,  Chi-Kuang Chen ,  Li Sha

Inventor： Hongjie Guan ,  Junqiang Lan ,  Yaojun Luo ,  Guan-Ming Su ,  Ching-Han Tsai ,  Chi-Kuang Chen ,  Li Sha

IPC: H04N11/02

CPC classification number: H04N19/423 ,  H04N19/44 ,  H04N19/91

Abstract: Devices, systems, methods, and other embodiments associated with a buffer controller are described. In one embodiment, an apparatus includes a buffer to buffer data. The apparatus further includes a status register and control logic. The control logic at least processes write commands. When the buffer is full and a write command to write data to the buffer is received, the control logic is configured to: accept the data without writing the data to the buffer, send an acknowledgment that the buffer was written, and set an overflow bit in the status register.

Abstract translation: 描述了与缓冲器控制器相关联的设备，系统，方法和其他实施例。 在一个实施例中，装置包括缓冲器以缓冲数据。 该装置还包括状态寄存器和控制逻辑。 控制逻辑至少处理写命令。 当缓冲区已满并且写入数据到缓冲区的写入命令被接收时，控制逻辑被配置为：接收数据而不将数据写入缓冲器，发送缓冲区被写入的确认，并设置溢出位 在状态寄存器中。

公开(公告)号：US08359420B2

公开(公告)日：2013-01-22

申请号：US12819451

申请日：2010-06-21

Applicant: Ching-Han Tsai ,  Cheng-Lun Chang ,  Jung-Tao Liu ,  Ya-Chau Yang

Inventor： Ching-Han Tsai ,  Cheng-Lun Chang ,  Jung-Tao Liu ,  Ya-Chau Yang

IPC: G06F13/28

CPC classification number: G06F15/163 ,  G06F15/17

Abstract: An external memory based FIFO (xFIFO) apparatus coupled to an external memory and a register bus is disclosed. The xFIFO apparatus includes an xFIFO engine, a wDMA engine, an rDMA engine, a first virtual FIFO, and a second virtual FIFO. The xFIFO engine receives a FIFO command from the register bus and generates a writing DMA command and a reading DMA command. The wDMA engine receives the writing DMA command from the xFIFO engine and forwards an incoming data to the external memory. The rDMA engine receives the reading DMA command from the xFIFO engine and pre-fetches a FIFO data from the external memory. The wDMA engine and the rDMA engine synchronize with each other via the first virtual FIFO and the second virtual FIFO.

Abstract translation: 公开了一种耦合到外部存储器和寄存器总线的基于外部存储器的FIFO（xFIFO）装置。 xFIFO装置包括xFIFO引擎，wDMA引擎，rDMA引擎，第一虚拟FIFO和第二虚拟FIFO。 xFIFO引擎从寄存器总线接收FIFO命令，并产生写入DMA命令和读取DMA命令。 wDMA引擎从xFIFO引擎接收写入DMA命令，并将传入的数据转发到外部存储器。 rDMA引擎从xFIFO引擎接收读取DMA命令，并从外部存储器中预取FIFO数据。 wDMA引擎和rDMA引擎通过第一虚拟FIFO和第二虚拟FIFO相互同步。

公开(公告)号：US08127058B1

公开(公告)日：2012-02-28

申请号：US12509800

申请日：2009-07-27

Applicant: Li Sha ,  Ching-Han Tsai ,  Chengjun Wang

Inventor： Li Sha ,  Ching-Han Tsai ,  Chengjun Wang

IPC: G06F3/00

CPC classification number: H04N19/433 ,  G06F5/065 ,  H04N19/426 ,  H04N19/44

Abstract: In one embodiment the present invention includes an apparatus having a random access memory, a first interface, and a second interface. The first interface is coupled between the random access memory and a plurality of storage devices, and operates in a first in first out (FIFO) manner. The second interface is coupled between the random access memory and a processor, and operates in a random access manner. As a result, the processor is not required to be in the loop when data is being transferred between the random access memory and the storage devices.

公开(公告)号：US07984211B2

公开(公告)日：2011-07-19

申请号：US12575446

申请日：2009-10-07

Applicant: Lincheng Wang ,  Ching-Han Tsai ,  Cheng-Lun Chang ,  Uma Shankar Durvasula ,  Jau-Wen Ren

Inventor： Lincheng Wang ,  Ching-Han Tsai ,  Cheng-Lun Chang ,  Uma Shankar Durvasula ,  Jau-Wen Ren

IPC: G06F3/00 ,  G06F5/00

CPC classification number: G06F13/4234 ,  G06F2213/0038 ,  H04N21/443

Abstract: A forced lock-step operation between a CPU (software) and the hardware is eliminated by unburdening the CPU from monitoring the hardware until it is finished with its task. This is done by providing a data/control message queue into which the CPU writes combined data/control messages and places an End tag into the queue when finished. The hardware checks the content of the message queue and starts decoding the incoming data. The hardware processes the data read from the message queue and the processed data is then written back into the message queue for use by the software. The hardware raises an interrupt signal to the CPU when reaching the End tag. Speed differences between hardware and software can be compensated for by changing the depth of the queue.

Abstract translation: CPU（软件）和硬件之间的强制锁定步骤操作通过卸载CPU来监视硬件直到完成任务来消除。 这通过提供一个数据/控制消息队列来完成，CPU写入组合的数据/控制消息，并在结束时将一个End标签放入队列。 硬件检查消息队列的内容，并开始对传入的数据进行解码。 硬件处理从消息队列读取的数据，然后处理的数据被写回到消息队列中供软件使用。 当达到End标签时，硬件会向CPU提供中断信号给CPU。 可以通过改变队列的深度来补偿硬件和软件之间的速度差异。

公开(公告)号：US09135006B1

公开(公告)日：2015-09-15

申请号：US13603958

申请日：2012-09-05

Applicant: Li Sha ,  Ching-Han Tsai ,  Chi-Kuang Chen ,  Tzun-Wei Lee

Inventor： Li Sha ,  Ching-Han Tsai ,  Chi-Kuang Chen ,  Tzun-Wei Lee

IPC: G06F9/32 ,  G06F9/30

CPC classification number: G06F9/30058 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/322 ,  G06F9/324 ,  G06F9/3806

Abstract: In accordance with the teachings described herein, systems and methods are provided for advanced execution of branch instructions in a microprocessor pipeline. In one embodiment, a branch instruction of an assembly language program code is executed that includes (i) a condition operand, (ii) a branch destination operand, and (iii) a program count operand. It is determined whether a current program count matches a stored program count operand. After determining that a condition was met when the branch instruction was executed, and in response to determining that the current program count matches the stored program count operand, a destination instruction specified by the stored branch destination operand is fetched.

Abstract translation: 根据本文所述的教导，提供了用于在微处理器管线中高级执行分支指令的系统和方法。 在一个实施例中，执行汇编语言程序代码的分支指令，其包括（i）条件操作数，（ii）分支目的地操作数和（iii）程序计数操作数。 确定当前程序计数是否与存储的程序计数操作数相匹配。 在确定在执行分支指令时满足条件之后，并且响应于确定当前程序计数与存储的程序计数操作数相匹配，获取由存储的分支目的地操作数指定的目的地指令。

公开(公告)号：US08811496B1

公开(公告)日：2014-08-19

申请号：US12511290

申请日：2009-07-29

Applicant: Yaojun Luo ,  Junqiang Lan ,  Hongjie Guan ,  Chi-Kuang Chen ,  Li Sha ,  Ching-Han Tsai

Inventor： Yaojun Luo ,  Junqiang Lan ,  Hongjie Guan ,  Chi-Kuang Chen ,  Li Sha ,  Ching-Han Tsai

IPC: H04N7/18 ,  H04N11/02 ,  H04N11/04

CPC classification number: H04N19/423 ,  H04N19/44 ,  H04N19/91

Abstract: Devices, systems, methods, and other embodiments associated with decoding image data are described. In one embodiment, an apparatus decoding a bitstream includes a parser that parses a command that includes instructions for decoding a syntax element bitstream from the bitstream. The parser functions to identify a number times to repeat the command and to identify a table associated with the syntax element bitstream based, at least in part, on a table identification (ID) in the command. A decoder decodes the syntax element bitstream as specified by the command based, at least in part, on retrieving a value in a table associated with the table ID to generate a syntax element.

Abstract translation: 描述了与解码图像数据相关联的设备，系统，方法和其他实施例。 在一个实施例中，解码比特流的装置包括分析器，其解析包括用于从比特流解码语法元素比特流的指令的命令。 解析器用于至少部分地基于命令中的表标识（ID）来识别重复该命令的次数并且识别与语法元素比特流相关联的表。 解码器至少部分地解码由命令所指定的语法元素比特流，该方法至少部分地检索与表ID相关联的表中的值以生成语法元素。