公开(公告)号：US08102267B1

公开(公告)日：2012-01-24

申请号：US12368290

申请日：2009-02-09

申请人： Darmindra D. Arumugam ,  Vijayakrishnan Ambravaneswaran ,  Daniel W. Engels

发明人： Darmindra D. Arumugam ,  Vijayakrishnan Ambravaneswaran ,  Daniel W. Engels

IPC分类号： G08B13/14

CPC分类号： G01S13/751 ,  G01S5/12

摘要： A single antenna single reader (SASR) system and method for locating a tag. The reader connects to a single antenna that is in motion. The reader transmits an interrogation signal to the tag. The reader receives a response signal from the tag. The reader determines the range of the tag from the reader, the received signal strength (RSS) of the response signal at the reader from the tag, and the maximum correlation of the response signal at the reader from the tag. The reader determines the location of the tag using range of the tag from the reader, received signal strength and maximum correlation of the response signal.

摘要翻译： 用于定位标签的单天线单读卡器（SASR）系统和方法。 阅读器连接到运动中的单个天线。 读取器向标签发送询问信号。 读卡器从标签接收响应信号。 读取器确定来自读取器的标签的范围，来自标签的读取器处的响应信号的接收信号强度（RSS）和读取器处的响应信号与标签的最大相关性。 阅读器使用来自读取器的标签的范围来确定标签的位置，接收信号强度和响应信号的最大相关性。

公开(公告)号：US08515059B2

公开(公告)日：2013-08-20

申请号：US13076357

申请日：2011-03-30

申请人： Daniel W. Engels ,  Kenneth Alan Lauffenburger ,  Eric Myron Smith ,  Troy Hicks

发明人： Daniel W. Engels ,  Kenneth Alan Lauffenburger ,  Eric Myron Smith ,  Troy Hicks

IPC分类号： H04L9/28

CPC分类号： G06F21/556 ,  G06F7/00 ,  G06F21/72 ,  G09C1/10 ,  H04L9/06

摘要： An efficient implementation of a cryptographic processor that dynamically updates the encryption state is described. The cryptographic processor can be implemented with a minimal number of gates, yet still perform cryptographic operations quickly. The cryptographic processor has an interface, a memory, a pseudorandom permutation block and control logic. The interface receives input data blocks and returns cryptographically processed data blocks. The memory is used to store an encryption state of the cryptographic processor. The pseudorandom permutation block transforms a portion of the encryption state that is modified for each input data block by at least the input data block and a previously transformed data block. The control logic routes data in the cryptographic processor to return cryptographically processed data blocks at the interface and update dynamically the encryption state stored in memory using the transformed data blocks from the pseudorandom permutation block.

摘要翻译： 描述了动态地更新加密状态的密码处理器的有效实现。 密码处理器可以用最少数量的门来实现，但仍然快速执行加密操作。 密码处理器具有接口，存储器，伪随机排列块和控制逻辑。 接口接收输入数据块并返回加密处理的数据块。 存储器用于存储加密处理器的加密状态。 伪随机置换块至少将输入数据块和先前变换的数据块变换为针对每个输入数据块修改的加密状态的一部分。 控制逻辑路由密码处理器中的数据，以在接口处返回加密处理的数据块，并使用来自伪随机置换块的变换数据块动态地更新存储在存储器中的加密状态。