公开(公告)号：US20090154442A1

公开(公告)日：2009-06-18

申请号：US12337702

申请日：2008-12-18

申请人： Jun-Kyu KANG ,  In-Tae Kang ,  Jeong-Gil Lee ,  Bo-Rham Lee ,  Sang-Min Bae

发明人： Jun-Kyu KANG ,  In-Tae Kang ,  Jeong-Gil Lee ,  Bo-Rham Lee ,  Sang-Min Bae

IPC分类号： H04B7/208

CPC分类号： H04L27/2614 ,  H03M1/662 ,  H03M1/70 ,  H04L5/0044 ,  H04L27/2626

摘要： A method and an apparatus for reducing Digital-to-Analog Conversion (DAC) bits at a transmitter of a Frequency Division Multiple Access (FDMA) system reduces a number of the bits for conversion so as to save power and reduce the cost of operation. The method can include generating a digital signal gain control value and an analog signal gain control value using subcarrier allocation information, a required Signal to Noise Ratio (SNR), and a Peak to Average Power Ratio (PAPR); controlling a gain of a signal input to a digital-to-analog converter using the digital signal gain control value; converting a digital signal of the controlled gain to an analog signal using the digital-to-analog converter; and restoring an original signal by controlling a gain of a signal output from the digital-to-analog converter using the analog signal gain control value.

摘要翻译： 用于减少频分多址（FDMA）系统的发射机处的数模转换（DAC）比特的方法和装置减少了用于转换的比特数，以节省功率并降低操作成本。 该方法可以包括使用子载波分配信息，所需的信噪比（SNR）和峰均功率比（PAPR）来产生数字信号增益控制值和模拟信号增益控制值; 使用数字信号增益控制值控制输入到数模转换器的信号的增益; 使用数模转换器将受控增益的数字信号转换为模拟信号; 以及通过使用模拟信号增益控制值控制从数模转换器输出的信号的增益来恢复原始信号。

公开(公告)号：US07998810B2

公开(公告)日：2011-08-16

申请号：US12424922

申请日：2009-04-16

申请人： Byung-hee Kim ,  Gil-heyun Choi ,  Sang-woo Lee ,  Chang-won Lee ,  Jin-ho Park ,  Eun-ji Jung ,  Jeong-gil Lee

发明人： Byung-hee Kim ,  Gil-heyun Choi ,  Sang-woo Lee ,  Chang-won Lee ,  Jin-ho Park ,  Eun-ji Jung ,  Jeong-gil Lee

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L29/66545

摘要： A method of forming a gate electrode of a semiconductor device is provided, the method including: forming a plurality of stacked structures each comprising a tunnel dielectric layer, a first silicon layer for floating gates, an intergate dielectric layer, a second silicon layer for control gates, and a mask pattern, on a semiconductor substrate in the stated order; forming a first interlayer dielectric layer between the plurality of stacked structures so that a top surface of the mask pattern is exposed; selectively removing the mask pattern of which the top surface is exposed; forming a third silicon layer in an area from which the hard disk layer was removed, and forming a silicon layer comprising the third silicon layer and the second silicon layer; recessing the first interlayer dielectric layer so that an upper portion of the silicon layer protrudes over the he first interlayer dielectric layer; and forming a metal silicide layer on the upper portion of the silicon layer.

摘要翻译： 提供一种形成半导体器件的栅电极的方法，所述方法包括：形成多个堆叠结构，每个堆叠结构包括隧道介电层，用于浮置栅极的第一硅层，栅极间介电层，用于控制的第二硅层 栅极和掩模图案，以所述顺序在半导体衬底上; 在所述多个堆叠结构之间形成第一层间电介质层，使得所述掩模图案的顶表面露出; 选择性地去除其顶表面暴露的掩模图案; 在去除所述硬盘层的区域中形成第三硅层，以及形成包含所述第三硅层和所述第二硅层的硅层; 使第一层间电介质层凹陷，使得硅层的上部突出在第一层间介电层上; 以及在所述硅层的上部形成金属硅化物层。

公开(公告)号：US07968410B2

公开(公告)日：2011-06-28

申请号：US12460945

申请日：2009-07-27

申请人： Eun-ji Jung ,  Sang-woo Lee ,  Jeong-gil Lee ,  Gil-heyun Choi ,  Chang-won Lee ,  Byung-hee Kim ,  Jin-ho Park

发明人： Eun-ji Jung ,  Sang-woo Lee ,  Jeong-gil Lee ,  Gil-heyun Choi ,  Chang-won Lee ,  Byung-hee Kim ,  Jin-ho Park

IPC分类号： H01L21/336

CPC分类号： H01L27/11573 ,  H01L21/28123 ,  H01L21/28282

摘要： A method of fabricating a semiconductor device includes: forming a first polysilicon layer having a first thickness in a peripheral circuit region formed on a substrate; forming a stack structure comprising a first tunneling insulating layer, a charge trap layer, and a blocking insulating layer in a memory cell region formed on the substrate; forming a second polysilicon layer having a second thickness that is less than the first thickness on the blocking insulating layer; and forming gate electrodes by siliciding the first and second polysilicon layers.

摘要翻译： 一种制造半导体器件的方法包括：在形成在衬底上的外围电路区域中形成具有第一厚度的第一多晶硅层; 在形成在所述基板上的存储单元区域中形成包括第一隧道绝缘层，电荷陷阱层和阻挡绝缘层的堆叠结构; 在所述阻挡绝缘层上形成具有小于所述第一厚度的第二厚度的第二多晶硅层; 以及通过硅化第一和第二多晶硅层来形成栅电极。