公开(公告)号：US06654943B2

公开(公告)日：2003-11-25

申请号：US09974984

申请日：2001-10-11

申请人： Joachim Gerhard Clabes ,  Thomas Edward Rosser

发明人： Joachim Gerhard Clabes ,  Thomas Edward Rosser

IPC分类号： G06F1750

CPC分类号： G06F17/505

摘要： A method, system, and computer product are disclosed for correcting anticipated problems related to global routing during logic synthesis. Synthesis is begun of a circuit design that includes multiple logic functions. During the synthesis, multiple logic books are selected to use to implement the logic function. Also during synthesis, at least one of the logic books is identified that is sensitive to a change in output wire capacitance of the identified logic book, where a value of the output wire capacitance is related to a routing of the wire. A strength of each identified logic book is then increased.

摘要翻译： 公开了一种方法，系统和计算机产品，用于在逻辑合成期间校正与全局路由相关的预期问题。 合成开始了包括多个逻辑功能的电路设计。 在合成期间，选择了多个逻辑书籍来实现逻辑功能。 此外，在合成期间，识别对识别的逻辑书的输出线电容的变化敏感的逻辑书中的至少一个，其中输出线电容的值与线的布线有关。 然后增加每个识别的逻辑书的强度。