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1.发明授权Method, system, and computer program product for improving wireability near dense clock nets 失效方法，系统和计算机程序产品，用于提高密集时钟网络附近的有线性公开(公告)号：US06728944B2
公开(公告)日：2004-04-27
申请号：US09998049
申请日：2001-11-29
IPC分类号： G06F1750
CPC分类号： G06F17/5072 , G06F17/5077
摘要： A method, system, and computer product are disclosed for improving wireability near clock nets in a logic design that includes multiple logic blocks. Each of the logic blocks has an actual physical size. Logic blocks that are a particular type are identified. During placement of the logic blocks, an apparent physical size of each of the identified logic blocks is utilized as a physical size for the identified logic block. The apparent physical size is larger than the actual physical size. During routing, the actual physical size of each of the identified logic blocks is utilized.
摘要翻译： 公开了一种用于在包括多个逻辑块的逻辑设计中改善靠近时钟网络的可线性的方法，系统和计算机产品。 每个逻辑块具有实际的物理大小。 识别出特定类型的逻辑块。 在放置逻辑块期间，每个识别的逻辑块的明显物理大小被用作所识别的逻辑块的物理大小。 表观物理尺寸大于实际物理尺寸。 在路由期间，利用每个识别的逻辑块的实际物理大小。
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公开(公告)号：US06922818B2
公开(公告)日：2005-07-26
申请号：US09833429
申请日：2001-04-12
申请人： Sam Gat-Shang Chu , Joachim Gerhard Clabes , Michael Normand Goulet , Thomas Edward Rosser , James Douglas Warnock
发明人： Sam Gat-Shang Chu , Joachim Gerhard Clabes , Michael Normand Goulet , Thomas Edward Rosser , James Douglas Warnock
CPC分类号： G06F17/505
摘要： A method and apparatus for reducing power consumption of a clocked circuit containing a plurality of latches is provided. A first latch, within the plurality of latches, is located which has more than a predetermined slack. The possibility of substituting an available second latch, that requires less power to operate, is then determined, subject to the constraint that the slack after substitution should still be positive, although it may be less than the predetermined number mentioned above. Where such a possibility is determined to exist, the first latch is then replaced with the available second latch.
摘要翻译： 提供了一种用于降低包含多个锁存器的时钟电路的功耗的方法和装置。 在多个闩锁内的第一闩锁被定位，其具有多于预定的松弛。 然后确定替代可用的第二锁存器的可能性，其需要更少的功率来操作，但是受到替代后的松弛仍然是正的限制，尽管它可能小于上述预定数量。 在确定存在这种可能性的情况下，然后用可用的第二锁存器替换第一锁存器。
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3.发明授权Method, system, and computer program product for correcting anticipated problems related to global routing 失效方法，系统和计算机程序产品，用于纠正与全局路由相关的预期问题公开(公告)号：US06654943B2
公开(公告)日：2003-11-25
申请号：US09974984
申请日：2001-10-11
IPC分类号： G06F1750
CPC分类号： G06F17/505
摘要： A method, system, and computer product are disclosed for correcting anticipated problems related to global routing during logic synthesis. Synthesis is begun of a circuit design that includes multiple logic functions. During the synthesis, multiple logic books are selected to use to implement the logic function. Also during synthesis, at least one of the logic books is identified that is sensitive to a change in output wire capacitance of the identified logic book, where a value of the output wire capacitance is related to a routing of the wire. A strength of each identified logic book is then increased.
摘要翻译： 公开了一种方法，系统和计算机产品，用于在逻辑合成期间校正与全局路由相关的预期问题。 合成开始了包括多个逻辑功能的电路设计。 在合成期间，选择了多个逻辑书籍来实现逻辑功能。 此外，在合成期间，识别对识别的逻辑书的输出线电容的变化敏感的逻辑书中的至少一个，其中输出线电容的值与线的布线有关。 然后增加每个识别的逻辑书的强度。
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公开(公告)号：US6035110A
公开(公告)日：2000-03-07
申请号：US761890
申请日：1996-12-09
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A certain type of gates, such as NOT gates, in a logic network are moved to the network boundary (i.e., inputs or outputs), at least in part, by selecting nodes in the network as candidate nodes for choosing among to determine output phase assignments. Such a candidate node is selected in response to non-reconvergence of branches fanning out from the node.
摘要翻译： 至少部分地，通过选择网络中的节点作为用于选择的候选节点来确定输出相位，逻辑网络中的某些类型的门（例如NOT门）被移动到网络边界（即，输入或输出） 作业。 响应于从节点扇出的分支的非重新收敛来选择这样的候选节点。
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5.发明申请TECHNIQUES FOR CALCULATING CIRCUIT BLOCK DELAY AND TRANSITION TIMES INCLUDING TRANSISTOR GATE CAPACITANCE LOADING EFFECTS 审中-公开计算电路块延迟和过渡时间的技术，包括晶闸管电容负载效应公开(公告)号：US20080177517A1
公开(公告)日：2008-07-24
申请号：US12055852
申请日：2008-03-26
IPC分类号： G06F17/11
CPC分类号： G06F17/5036
摘要： Techniques for modeling delay and transition times of logical circuit blocks including transistor gate capacitance loading effects provides improved simulation of logical circuit block transition times and delay times. The non-linear behavior of transistor gates of other logical circuit block inputs that are connected to the logical circuit block output is taken into account by a transition time function and a delay time function that are each separately dependent on static capacitance and transistor gate capacitance and can be used to determine logical circuit block timing and output performance. A separate N-channel and P-channel gate capacitance may also be used as inputs to the transition time and delay time functions to provide further improvement, or a ratio of N-channel to P-channel capacitances may alternatively be used as input to the transition time and delay time functions.
摘要翻译： 用于建模包括晶体管栅极电容负载效应的逻辑电路块的延迟和转换时间的技术提供了逻辑电路块转换时间和延迟时间的改进的仿真。 通过转换时间函数和延迟时间函数考虑连接到逻辑电路块输出的其他逻辑电路块输入的晶体管栅极的非线性行为，其分别取决于静态电容和晶体管栅极电容， 可用于确定逻辑电路块的时序和输出性能。 单独的N沟道和P沟道栅极电容也可以用作转换时间和延迟时间函数的输入以提供进一步的改进，或者N沟道与P沟道电容的比率可以替代地用作 转换时间和延迟时间功能。
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公开(公告)号：US06282695B1
公开(公告)日：2001-08-28
申请号：US09213320
申请日：1998-12-16
IPC分类号： G06F1700
CPC分类号： G06F17/505
摘要： A redesigning of dynamic logic circuitry inputs into a process implemented in a computer the dynamic logic circuitry to be redesigned as a set of boolean equations. Along a path through the logic circuitry, the logic circuitry is converted into AND and OR books, or blocks of circuitry. Then various portions of these books are compared to a library of AND/OR and OR/AND books. A list of these possible substitutions from the comparison step is produced. From the list, a selection process selects those substitutions providing a best cost benefit.
摘要翻译： 将动态逻辑电路输入重新设计为在计算机中实现的过程中的动态逻辑电路，以被重新设计为一组布尔方程。 沿着通过逻辑电路的路径，逻辑电路被转换为AND和OR书籍或电路块。 然后将这些书的各个部分与AND / OR和OR / AND图书馆进行比较。 产生来自比较步骤的这些可能取代的列表。 从列表中，选择过程选择提供最佳成本效益的替代。
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公开(公告)号：US5903467A
公开(公告)日：1999-05-11
申请号：US763980
申请日：1996-12-10
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： In designing a logic network a plurality of nodes are identified which define incompatible output phase assignments. Certain of the incompatible nodes are selected for assigning the output phases, so that NOT gates in the fan-out cone of such a selected node are moved to the network outputs. In a further aspect, the selecting is in response to the number of logic gates in the fan-in cones of the incompatible nodes.
摘要翻译： 在设计逻辑网络时，识别出定义不兼容的输出相位分配的多个节点。 选择某些不兼容的节点用于分配输出相位，使得这样选择的节点的扇出锥的NOT门被移动到网络输出。 在另一方面，该选择是响应于不兼容节点的扇入锥中的逻辑门数。
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8.发明授权Method and system for modeling logical circuit blocks including transistor gate capacitance loading effects 失效对逻辑电路块进行建模的方法和系统，包括晶体管栅极电容负载效应公开(公告)号：US07552040B2
公开(公告)日：2009-06-23
申请号：US10366439
申请日：2003-02-13
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method and system for modeling logical circuit blocks including transistor gate capacitance loading effects provides improved simulation of logical circuit block transition times and delay times. The non-linear behavior of transistor gates of other logical circuit block inputs that are connected to the logical circuit block output is taken into account by a transition time function and a delay time function that are each separately dependent on static capacitance and transistor gate capacitance and can be used to determine logical circuit block timing and output performance. A separate N-channel and P-channel gate capacitance may also be used as inputs to the transition time and delay time functions to provide further improvement, or a ratio of N-channel to P-channel capacitances may alternatively be used as input to the transition time and delay time functions.
摘要翻译： 用于对包括晶体管栅极电容负载效应的逻辑电路块进行建模的方法和系统提供了对逻辑电路块转换时间和延迟时间的改进的仿真。 通过转换时间函数和延迟时间函数考虑连接到逻辑电路块输出的其他逻辑电路块输入的晶体管栅极的非线性行为，其分别取决于静态电容和晶体管栅极电容， 可用于确定逻辑电路块的时序和输出性能。 单独的N沟道和P沟道栅极电容也可以用作转换时间和延迟时间函数的输入以提供进一步的改进，或者N沟道与P沟道电容的比率可以替代地用作 转换时间和延迟时间功能。
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公开(公告)号：US6018621A
公开(公告)日：2000-01-25
申请号：US761891
申请日：1996-12-09
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： At least one certain type of logic gates, such as NOT gates, in a network of logic gates are moved to the network inputs and outputs, by converting the logic gates in the network to certain types of gates, such as AND, OR and NOT gates. A region in the network is identified for selecting, within the region, between propagating the one certain type of gates to a) the network inputs, and b) the network outputs. The region is identified in response to "reconvergent fanout nodes". A reconvergent fanout node defines a loop having two branches which diverge at the node and reconverge thereafter.
摘要翻译： 通过将网络中的逻辑门转换为某些类型的门，例如AND，OR和NOT，逻辑门网络中的至少一种某种类型的逻辑门（例如NOT门）被移动到网络输入和输出 大门 网络中的区域被识别用于在区域内选择传播一种特定类型的门到a）网络输入，以及b）网络输出。 响应于“重新启动扇出节点”识别该区域。 再聚合扇出节点定义了一个具有两个分支的循环，该分支在节点处发散，此后重新收敛。
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10.发明授权Method and apparatus for detecting and correcting inaccuracies in curve-fitted models 失效用于检测和纠正曲线拟合模型中的不准确度的方法和装置公开(公告)号：US07194394B2
公开(公告)日：2007-03-20
申请号：US09999141
申请日：2001-11-15
IPC分类号： G06G7/48
CPC分类号： G06F17/17
摘要： A technique for detecting and correcting inaccuracies in curve-fitted models. Humps and dips in a curve-fitted model are identified. An analysis is performed on the humps and dips to determine if they are large enough to warrant correction. If so, then the source of the simulation and/or empirical data is modified to taking corrective action to improve the curve fit between the edge point and the next actual simulation and/or empirical data point.
摘要翻译： 一种用于检测和校正曲线拟合模型中的不准确度的技术。 识别曲线拟合模型中的臀部和臀部。 对隆起和下降进行分析，以确定它们是否足够大以保证校正。 如果是这样，那么模拟和/或经验数据的来源被修改以采取纠正措施来改善边缘点和下一个实际模拟和/或经验数据点之间的曲线拟合。
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