公开(公告)号：US20240303056A1

公开(公告)日：2024-09-12

申请号：US18595911

申请日：2024-03-05

Applicant: MOREH CORP.

Inventor： Gangwon Jo ,  Jungho Park

IPC: G06F8/41

CPC classification number: G06F8/4441

Abstract: A method for compiling an application is executed by one or more processors, and includes acquiring profiling information of a system on which an application is to be executed, generating a cost model based on the profiling information, acquiring an intermediate representation of at least a portion of the application, applying compiler passes to the intermediate representation and generating a compiled graph, and using the cost model, determining an expected execution time for the compiled graph.

公开(公告)号：US20240303053A1

公开(公告)日：2024-09-12

申请号：US18595822

申请日：2024-03-05

Applicant: MOREH CORP

Inventor： Gangwon Jo ,  Jungho Park

IPC: G06F8/41

CPC classification number: G06F8/443

Abstract: The disclosure relates to a method for compiling an application, in which the method is executed by one or more processors, and includes initiating generating a first intermediate representation for a first part of an application, while generating the first intermediate representation, stopping generating the first intermediate representation if it is determined that a number of operation nodes included in the first intermediate representation reaches an interval value, and compiling the generated first intermediate representation.

公开(公告)号：US20240303051A1

公开(公告)日：2024-09-12

申请号：US18595962

申请日：2024-03-05

Applicant: Moreh Corp.

Inventor： Gangwon Jo ,  Jungho Park

IPC: G06F8/41

CPC classification number: G06F8/41

Abstract: A method for compiling an application is executed by one or more processors, and includes acquiring profiling information of a system on which an application is to be executed, generating a cost model based on the profiling information, acquiring an intermediate representation of at least a portion of the application, applying compiler passes to the intermediate representation and generating a compiled graph, and using the cost model, determining an expected execution time for the compiled graph.

公开(公告)号：US20240126790A1

公开(公告)日：2024-04-18

申请号：US18537683

申请日：2023-12-12

Applicant: MOREH CORP. ,  SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION

Inventor： Jaejin LEE ,  Jungho PARK ,  Gangwon JO ,  Heehoon KIM ,  Jinpyo KIM

IPC: G06F16/28 ,  G06F16/23 ,  G06F16/25

CPC classification number: G06F16/287 ,  G06F16/23 ,  G06F16/254

Abstract: A method for creating an intermediate representation is performed by one or more processors and includes by an intermediate representation creation unit, extracting, from the program, information on data for input and output and information on operation, by the intermediate representation creation unit, determining the presence or absence of an in-place operation based on the extracted information on data and the extracted information on operation, and by the intermediate representation creation unit, if there is the in-place operation, creating an intermediate representation using the extracted information on data, the extracted information on operation, and a creation rule associated with the in-place operation, in which input data of the in-place operation is data that is replaced with output data after the in-place operation.

公开(公告)号：US20230031226A1

公开(公告)日：2023-02-02

申请号：US17964626

申请日：2022-10-12

Applicant: MOREH CORP.

Inventor： Jaejin Lee ,  Jungho Park ,  Youngdong Do

IPC: G06N3/08

Abstract: Provided is a method for processing a deep learning task through a deep learning framework. The method may include executing, by a computing device, a deep learning task on a deep learning framework, determining at least one of a primary accelerator or a secondary accelerator to execute the deep learning task, allocating the deep learning task to at least one of the determined primary accelerator or secondary accelerator, and generating, based on a result processed by at least one of the determined primary accelerator or secondary accelerator, result data for the deep learning task. The secondary accelerator may be an accelerator heterogeneous to the primary accelerator.

公开(公告)号：US20240303155A1

公开(公告)日：2024-09-12

申请号：US18596818

申请日：2024-03-06

Applicant: MOREH CORP.

Inventor： Gangwon Jo ,  Jungho Park

IPC: G06F11/07

CPC classification number: G06F11/0793

Abstract: Provided is a fault tolerance method which is performed by one or more processors, and which includes receiving an application execute command, executing a main process of an application in response to the execute command, receiving, by a split execution module, information on a plurality of devices associated with the execution of the application from an orchestrator, executing, by the split execution module, a sub-process for each of the plurality of devices using the information on the plurality of devices, and performing, by the split execution module, fault tolerance associated with the execution of the application using an idle device, if a failure occurs in at least some of the plurality of devices.

公开(公告)号：US20240303125A1

公开(公告)日：2024-09-12

申请号：US18418994

申请日：2024-01-22

Applicant: MOREH CORP.

Inventor： Gangwon Jo ,  Jungho Park

IPC: G06F9/50 ,  G06F11/34

CPC classification number: G06F9/5038 ,  G06F11/3466

Abstract: Provided is a method for creating an operation call list for artificial intelligence calculation, which is performed by one or more processors, and includes acquiring a trace from a source program including an artificial intelligence calculation, wherein the trace includes at least one of code or primitive operation associated with the source program, and creating a call list including a plurality of primitive operations based on the trace, in which the plurality of primitive operations may be included in an operation library accessible to each of the plurality of accelerators.

公开(公告)号：US20240303083A1

公开(公告)日：2024-09-12

申请号：US18423642

申请日：2024-01-26

Applicant: MOREH CORP.

Inventor： Gangwon Jo ,  Jungho Park

IPC: G06F9/38

CPC classification number: G06F9/3836

Abstract: A method for compiling for overlapping instructions between a plurality of processors is provided, which is performed by one or more processors, and includes receiving a source program, determining a plurality of instructions to be executed in the plurality of processors based on the source program, and assigning the plurality of instructions to the plurality of processors such that a first portion of the plurality of instructions and a second portion of the plurality of instructions are processed in parallel by each of the plurality of processors.

公开(公告)号：US20240303054A1

公开(公告)日：2024-09-12

申请号：US18426983

申请日：2024-01-30

Applicant: MOREH CORP.

Inventor： Gangwon Jo ,  Jungho Park

IPC: G06F8/41

CPC classification number: G06F8/4434

Abstract: A method for compilation optimization using activation recalculation is provided, which is performed by one or more processors, and includes receiving a source program, determining an operation to be executed in a processor based on the source program, and determining whether or not the operation to be executed corresponds to the operation for activation recalculation, thereby automatically classifying the operation to be executed into a first operation type corresponding to the operation for activation recalculation or a second operation type not corresponding to the operation for activation recalculation.

公开(公告)号：US20240103877A1

公开(公告)日：2024-03-28

申请号：US18533041

申请日：2023-12-07

Applicant: MOREH CORP. ,  SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION

Inventor： Jaejin LEE ,  Jungho PARK ,  Gangwon JO ,  Heehoon KIM ,  Jinpyo KIM

IPC: G06F9/38

CPC classification number: G06F9/3836

Abstract: A method for generating an intermediate representation for a program for execution on an accelerator is executed by one or more processors, and includes hooking information on instruction from a program, determining whether the hooked information on instruction is associated with an accelerator, if it is determined that the information on instruction is associated with the accelerator, generating a first intermediate representation for the instruction using information on input and output data and information on instruction included in the instruction, and generating a second intermediate representation for the program for one or more accelerators using the first intermediate representation, and the first intermediate representation and the second intermediate representation include a plurality of data nodes, one or more operation nodes, and a plurality of edges indicating an input and output relationship between the plurality of data nodes and the one or more operation nodes.