公开(公告)号：US08532975B2

公开(公告)日：2013-09-10

申请号：US12814350

申请日：2010-06-11

Applicant: Mitchell Poplack ,  Beshara Elmufdi

Inventor： Mitchell Poplack ,  Beshara Elmufdi

IPC: G06F9/455

CPC classification number: G06F17/5022 ,  G06F11/261 ,  G06F17/5027 ,  G06F17/5045

Abstract: A system and method for capturing and delivering emulation data from a hardware emulation system to a simulator running on a host workstation without considerably sacrificing emulation speed or sacrificing the emulation capacity available for a user's logic design. According to one embodiment, a system, comprises a logic software simulator running on a host workstation; a hardware emulation system having a system bus and an emulator chip, the emulator chip includes: an emulation processor cluster, and a capture buffer connected to the system bus; and a high-speed interface connecting the host workstation to the system bus of the hardware emulator, wherein the capture buffer captures a select output of the emulation processor cluster.

Abstract translation: 一种用于从硬件仿真系统捕获并将仿真数据传送到在主机工作站上运行的仿真器的系统和方法，而不会极大地牺牲仿真速度或牺牲用户逻辑设计可用的仿真能力。 根据一个实施例，系统包括在主机工作站上运行的逻辑软件模拟器; 具有系统总线和仿真器芯片的硬件仿真系统，仿真器芯片包括：仿真处理器集群和连接到系统总线的捕获缓冲器; 以及将主机工作站连接到硬件仿真器的系统总线的高速接口，其中捕获缓冲器捕获仿真处理器集群的选择输出。

公开(公告)号：US20070239422A1

公开(公告)日：2007-10-11

申请号：US11401641

申请日：2006-04-11

Applicant: Mikhail Bershteyn ,  Mitchell Poplack ,  Beshara Elmufdi

Inventor： Mikhail Bershteyn ,  Mitchell Poplack ,  Beshara Elmufdi

IPC: G06F9/455

CPC classification number: G06F17/5027

Abstract: A hardware emulation system having a heterogeneous cluster of processors is described. The apparatus for emulating a hardware design comprises a plurality of processors, where each processor performs a different function during an emulation cycle. The method performed by the apparatus comprises using a data fetch processor to retrieve data from a data array, evaluating the retrieved data using the data fetch processor to produce an output bit, supplying the output bit to an intracluster crossbar and using a data store processor to store the output bit in the data array.

Abstract translation: 描述了具有异构的处理器簇的硬件仿真系统。 用于模拟硬件设计的装置包括多个处理器，其中每个处理器在仿真周期期间执行不同的功能。 由该装置执行的方法包括使用数据提取处理器从数据阵列中检索数据，使用数据获取处理器评估所检索的数据以产生输出比特，将输出比特提供给群内交叉开关并使用数据存储处理器 将输出位存储在数据数组中。

公开(公告)号：US20050278163A1

公开(公告)日：2005-12-15

申请号：US11141141

申请日：2005-05-31

Applicant: Mitchell Poplack ,  John Maher

Inventor： Mitchell Poplack ,  John Maher

IPC: G06F9/455

CPC classification number: G06F11/261

Abstract: A signal conversion system for interfacing selected components of a communication system and methods for manufacturing and using same. The signal conversion system converts selected logic signals from one system component into a pair of differential logic signals and provides the pair of differential logic signals to a second system component, resolving any logical and/or temporal artifacts. While one or more of the selected logic signals change signal state, the signal conversion system maintains the pair of differential logic signals in a first valid combined signal state until the signal state of the selected logic signals corresponds to a second valid combined signal state for the pair of differential logic signals. The signal verification system then updates the pair of differential logic signals to have the second valid combined signal state. The system components thereby can communicate, exchanging differential communication signals while maintaining duty cycle and avoiding signaling glitches.

Abstract translation: 一种用于连接通信系统的选定组件的信号转换系统及其制造和使用方法。 信号转换系统将所选逻辑信号从一个系统组件转换成一对差分逻辑信号，并将一对差分逻辑信号提供给第二系统组件，以解决任何逻辑和/或时间假象。 当所选逻辑信号中的一个或多个改变信号状态时，信号转换系统将该对差分逻辑信号维持在第一有效组合信号状态，直到所选逻辑信号的信号状态对应于第二有效组合信号状态 差分逻辑信号对。 信号验证系统然后更新该对差分逻辑信号以具有第二有效组合信号状态。 因此，系统组件可以通信，交换差分通信信号，同时保持占空比并避免信令故障。

公开(公告)号：US20050266709A1

公开(公告)日：2005-12-01

申请号：US11062047

申请日：2005-02-18

Applicant: Catalino Datan ,  Mitchell Poplack

Inventor： Catalino Datan ,  Mitchell Poplack

IPC: H01R13/62 ,  H01R13/633

CPC classification number: H01R12/7005

Abstract: A mechanism is described for effecting the ejection of a high extraction force electromechanical connector from its mate by utilizing an ejector mechanism and without requiring custom design or manufacturing of the mating connector. One embodiment achieves this by way of rigid sliding frame which applies force to a portion of the mating connector which is otherwise intended to provide alignment guidance between the two connectors.

Abstract translation: 描述了一种机构，用于通过利用喷射器机构实现高吸力机电连接器的喷射，而不需要定制设计或配制连接器的制造。 一个实施例通过刚性滑动框架来实现，该刚性滑动框架对配合连接器的一部分施加力，否则其旨在在两个连接器之间提供对准引导。