公开(公告)号：US20050267727A1

公开(公告)日：2005-12-01

申请号：US11140714

申请日：2005-05-31

申请人： Mitchell Poplack ,  John Maher

发明人： Mitchell Poplack ,  John Maher

IPC分类号： G06F9/455

CPC分类号： H04L43/50

摘要： A target interface system for flexibly routing and timing communication signals exchanged between selected components of a communication system and methods for manufacturing and using same. Under the control of a host system, the target interface system samples an output data signal provided by the host system and includes a reconfigurable datapath for flexibly routing the sampled data signal to a selected target I/O pin of the target interface system. The selected target I/O pin provides the sampled data signal as an outgoing target data signal to a target system and likewise receives an incoming target data signal from the target system. Upon sampling the incoming target data signal, the target interface system flexibly routes the sampled data signal to the host system as an input data signal. The target interface system thereby facilitates exchanges of communication signals between the host system and the target system.

摘要翻译： 用于在通信系统的选定组件之间交换的灵活路由和定时通信信号的目标接口系统及其制造和使用方法。 在主机系统的控制下，目标接口系统对由主机系统提供的输出数据信号进行采样，并且包括用于将采样数据信号灵活地路由到目标接口系统的选定目标I / O引脚的可重构数据通路。 所选择的目标I / O引脚将采样的数据信号作为输出目标数据信号提供给目标系统，同样从目标系统接收输入的目标数据信号。 在对输入目标数据信号进行采样时，目标接口系统将采样的数据信号灵活地路由到主机系统作为输入数据信号。 因此，目标接口系统便于主机系统和目标系统之间的通信信号的交换。

公开(公告)号：US09069918B2

公开(公告)日：2015-06-30

申请号：US12814337

申请日：2010-06-11

申请人： Mitchell Poplack ,  Beshara Elmufdi

发明人： Mitchell Poplack ,  Beshara Elmufdi

IPC分类号： G06F9/455 ,  G06F17/50 ,  G06F11/26

CPC分类号： G06F17/5022 ,  G06F11/261 ,  G06F17/5027 ,  G06F17/5045

摘要： A system and method for writing simulation acceleration data from a host workstation to a hardware emulation system without considerably sacrificing emulation speed or sacrificing the emulation capacity available for a user's logic design. According to one embodiment, a system comprises a logic software simulator running on a host workstation; a hardware emulation system having a system bus and an emulator chip, the emulator chip includes: an emulation processor that generates emulation data, and a data array connected to the system bus; and a high-speed interface connecting the host workstation to the system bus of the hardware emulator, wherein simulation acceleration data from the host workstation are written to the data array of the emulator chip using the system bus.

摘要翻译： 用于将模拟加速数据从主机工作站写入硬件仿真系统的系统和方法，而不会极大地牺牲仿真速度或牺牲用户逻辑设计可用的仿真能力。 根据一个实施例，系统包括在主机工作站上运行的逻辑软件模拟器; 具有系统总线和仿真器芯片的硬件仿真系统，所述仿真器芯片包括：产生仿真数据的仿真处理器和连接到所述系统总线的数据阵列; 以及将主机工作站连接到硬件仿真器的系统总线的高速接口，其中使用系统总线将来自主机工作站的仿真加速数据写入仿真器芯片的数据阵列。

公开(公告)号：US20050267729A1

公开(公告)日：2005-12-01

申请号：US11141599

申请日：2005-05-31

申请人： Mitchell Poplack ,  John Maher

发明人： Mitchell Poplack ,  John Maher

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5027

摘要： A target interface system for interfacing selected components of a communication system and methods for manufacturing and using same. The target interface system includes target interface logic that is distributed among a plurality of reconfigurable logic devices. Being coupled via a serial link, the reconfigurable logic devices each have an input connection for receiving incoming data packets and an output connection for providing outgoing data packets. The serial link couples the input and output connections of successive reconfigurable logic devices to form a dataring structure for distributing the data packets among the reconfigurable logic devices. Thereby, the dataring structure maintains data synchronization among the reconfigurable logic devices such that the distribution of the target interface logic among the reconfigurable logic devices is transparent to software.

摘要翻译： 用于连接通信系统的选定组件的目标接口系统及其制造和使用方法。 目标接口系统包括分布在多个可重新配置的逻辑设备中的目标接口逻辑。 通过串行链路耦合，可重配置逻辑器件每个都具有用于接收输入数据分组的输入连接和用于提供输出数据分组的输出连接。 串行链路将连续的可重构逻辑设备的输入和输出连接耦合以形成用于在可重新配置的逻辑设备之间分配数据分组的数据结构。 因此，数据结构维持可重构逻辑设备之间的数据同步，使得可重构逻辑设备中的目标接口逻辑的分布对于软件是透明的。

公开(公告)号：US20050267728A1

公开(公告)日：2005-12-01

申请号：US11140722

申请日：2005-05-31

申请人： John Maher ,  Mitchell Poplack

发明人： John Maher ,  Mitchell Poplack

IPC分类号： G06F9/455 ,  G06F13/38

CPC分类号： G06F13/387

摘要： A target interface system for interfacing selected components of a communication system and methods for manufacturing and using same. Being reconfigurable to support an extensive range of conventional input/output technologies, the target interface system downloads a selected image associated with a desired input/output technology prior to runtime. The selected image identifies an appropriate output driver supply voltage, and any auxiliary voltages are controlled as functions of the output driver supply voltage to limit voltage inconsistencies. Defaulting each voltage to its least dangerous state when unprogrammed, the target interface system subsequently monitors the voltages, disabling the input/output connections if a problem is detected. The target interface system likewise detects when a selected system component is absent, unpowered, and/or wrongly powered and provides contention detection. Thereby, the target interface system can facilitate communication among the system components while inhibiting damage to the target interface system and/or the system components.

摘要翻译： 用于连接通信系统的选定组件的目标接口系统及其制造和使用方法。 可重新配置以支持广泛的常规输入/输出技术，目标接口系统在运行之前下载与所需输入/输出技术相关联的所选图像。 所选择的图像识别适当的输出驱动器电源电压，并且任何辅助电压被控制为输出驱动器电源电压的功能，以限制电压不一致。 当未编程时，将每个电压默认为最低危险状态，目标接口系统随后监控电压，如果检测到问题，则禁用输入/输出连接。 目标接口系统同样检测所选择的系统组件何时不存在，无电源和/或错误地供电并提供争用检测。 因此，目标接口系统可以促进系统组件之间的通信，同时抑制对目标接口系统和/或系统组件的损坏。

公开(公告)号：US20070179772A1

公开(公告)日：2007-08-02

申请号：US11344766

申请日：2006-02-01

申请人： William Beausoleil ,  Beshara Elmufdi ,  Mitchell Poplack ,  Tai Su

发明人： William Beausoleil ,  Beshara Elmufdi ,  Mitchell Poplack ,  Tai Su

IPC分类号： G06F9/455

CPC分类号： G06F17/5022

摘要： A method and apparatus for a memory efficient hardware emulator. The emulator comprises a plurality of processor dusters having data within the duster is stored in at least one data array, where the at least one data array comprises a plurality of sub-arrays. The sub-arrays that are not of uniform size (e.g., the size of each sub-array is determined by the probability that a particular sub-array will be accessed by the processor during a future emulation step). For example, at least one first sub-array is equal in depth to instruction memory within a processor (i.e., equal to the number of instructions in an emulation cycle), and the remaining sub-arrays are a fractional depth of the first sub-array.

摘要翻译： 一种用于存储器高效硬件仿真器的方法和装置。 模拟器包括多个处理器喷粉器，其中除尘器内的数据被存储在至少一个数据阵列中，其中至少一个数据阵列包括多个子阵列。 不均匀大小的子阵列（例如，每个子阵列的大小由在未来仿真步骤期间由处理器访问特定子阵列的概率确定）。 例如，至少一个第一子阵列在处理器内的深度与指令存储器相等（即，等于仿真周期中的指令数），而其余的子阵列是第一子阵列的分数深度， 数组。

公开(公告)号：US20060190237A1

公开(公告)日：2006-08-24

申请号：US11321201

申请日：2005-12-29

申请人： William Beausoleil ,  Mitchell Poplack ,  Steven Comfort ,  Beshara Elmufdi

发明人： William Beausoleil ,  Mitchell Poplack ,  Steven Comfort ,  Beshara Elmufdi

IPC分类号： G06F9/455

CPC分类号： G06F17/5022 ,  G06F2217/86

摘要： The present system and methods are directed to the interconnection of clusters of emulation processors comprising emulation processors in a software-driven hardware design verification system. The processors each output one NBO output signal. The clusters are interconnected by partitioning a common NBO bus into a number of smaller NBO busses, each carrying unique NBO signals but together carrying every NBO. Each of the smaller NBO busses are passed into a series of multiplexers, each dedicated to a particular processor. The multiplexers select a signal for output back to the emulation clusters. The multiplexers that handle these smaller NBO busses are narrower than was previously required, thus reducing the amount of power, interconnect, and area required by the multiplexer array and dedicated interconnect.

公开(公告)号：US20050271078A1

公开(公告)日：2005-12-08

申请号：US10992165

申请日：2004-11-17

申请人： Barton Quayle ,  Mitchell Poplack ,  Peter Tannenbaum

发明人： Barton Quayle ,  Mitchell Poplack ,  Peter Tannenbaum

IPC分类号： G06F17/50 ,  H04L12/50 ,  H04L25/02

CPC分类号： G06F17/5027 ,  H04L25/0272

摘要： An identification system for identifying and validating selected components of a communication system and methods for manufacturing and using same. The communication system includes a host system that is configured to couple with one or more target systems. When the host system is coupled with a selected target system, the communication system can enter an identification mode wherein the selected target system can provide identification data to the host system. The identification data includes information regarding at least one target system characteristic associated with the selected target system such that the host system can attempt to identify the selected target system based at least in part upon the target system characteristics. Once the selected target system has been identified, the communication system likewise can at least partially reconfigure the host system, as necessary, such that the host system can be compatible with the selected target system.

摘要翻译： 用于识别和验证通信系统的选定组件的识别系统及其制造和使用方法。 通信系统包括被配置为与一个或多个目标系统耦合的主机系统。 当主机系统与所选择的目标系统耦合时，通信系统可以进入识别模式，其中所选择的目标系统可以向主机系统提供识别数据。 识别数据包括关于与所选择的目标系统相关联的至少一个目标系统特征的信息，使得主机系统可以至少部分地基于目标系统特性来尝试识别所选择的目标系统。 一旦所选择的目标系统被识别，通信系统同样可以根据需要至少部分地重新配置主机系统，使得主机系统可以与所选择的目标系统兼容。

公开(公告)号：US20050265375A1

公开(公告)日：2005-12-01

申请号：US10992588

申请日：2004-11-17

申请人： Barton Quayle ,  Mitchell Poplack ,  Peter Tannenbaum

发明人： Barton Quayle ,  Mitchell Poplack ,  Peter Tannenbaum

IPC分类号： H04L12/24 ,  H04L12/403

CPC分类号： H04L41/0803 ,  H04L41/0866 ,  H04L41/145

摘要： An identification system for identifying and validating selected components of a communication system and methods for manufacturing and using same. The communication system includes a host system that is configured to couple with one or more target systems. When the host system is coupled with a selected target system, the communication system can enter an identification mode wherein the selected target system can provide identification data to the host system. The identification data includes information regarding at least one target system characteristic associated with the selected target system such that the host system can attempt to identify the selected target system based at least in part upon the target system characteristics. Once the selected target system has been identified, the communication system likewise can at least partially reconfigure the host system, as necessary, such that the host system can be compatible with the selected target system.

摘要翻译： 用于识别和验证通信系统的选定组件的识别系统及其制造和使用方法。 通信系统包括被配置为与一个或多个目标系统耦合的主机系统。 当主机系统与所选择的目标系统耦合时，通信系统可以进入识别模式，其中所选择的目标系统可以向主机系统提供识别数据。 识别数据包括关于与所选择的目标系统相关联的至少一个目标系统特征的信息，使得主机系统可以至少部分地基于目标系统特性来尝试识别所选择的目标系统。 一旦所选择的目标系统被识别，通信系统同样可以根据需要至少部分地重新配置主机系统，使得主机系统可以与所选择的目标系统兼容。

公开(公告)号：US20050114113A1

公开(公告)日：2005-05-26

申请号：US10975676

申请日：2004-10-28

申请人： Barton Quayle ,  Mitchell Poplack

发明人： Barton Quayle ,  Mitchell Poplack

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5027 ,  G06F17/5022 ,  G06F2217/86

摘要： An optimized interface for simulation and visualization data transfer between an emulation system and simulator is disclosed. In one embodiment, a method of transferring data between a simulator to an emulator across an interface, comprises updating a simulator buffer of the simulator to contain a desired input state for an emulation cycle. A target write to the interface is performed to indicate that the emulation cycle can proceed. The emulation cycle is completed using an instruction sequencer within the interface independent of the simulator.

摘要翻译： 公开了一种用于仿真系统和仿真器之间的仿真和可视化数据传输的优化接口。 在一个实施例中，一种在仿真器之间通过接口传输数据的方法包括更新模拟器的模拟器缓冲器以包含用于仿真周期的期望输入状态。 执行对该接口的目标写入，以指示仿真循环可以继续进行。 使用独立于模拟器的接口内的指令序列器来完成仿真周期。

公开(公告)号：US09015026B2

公开(公告)日：2015-04-21

申请号：US12814333

申请日：2010-06-11

申请人： Mitchell Poplack

发明人： Mitchell Poplack

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5022 ,  G06F11/261 ,  G06F17/5027 ,  G06F17/5045

摘要： A system and method for verifying logic circuit designs having arithmetic operations and complex logical operations such that the operations may be evaluated at substantially full hardware speed is disclosed. According to one embodiment, a system for verifying the functionalities of an electronic circuit design comprises hardware emulation resources emulating at least a portion of an electronic circuit design; and a first hardware ALU block having an arithmetic logic unit that performs an arithmetic operation or a complex logical operation of the electronic circuit design, and a set of flag registers that contains a conditional value for enabling the arithmetic logic unit.

摘要翻译： 公开了一种用于验证具有算术运算和复杂逻辑运算的逻辑电路设计的系统和方法，使得可以以基本上全硬件速度来评估操作。 根据一个实施例，用于验证电子电路设计的功能的系统包括模拟电子电路设计的至少一部分的硬件仿真资源; 以及具有执行电子电路设计的算术运算或复杂逻辑运算的算术逻辑单元的第一硬件ALU块和包含用于使能算术逻辑单元的条件值的一组标志寄存器。