公开(公告)号：US20110219210A1

公开(公告)日：2011-09-08

申请号：US13106042

申请日：2011-05-12

申请人： Gerald G. Pechanek ,  David Carl Strube ,  Edwin Frank Barry ,  Charles W. Kurak, JR. ,  Carl Donald Busboom ,  Dale Edward Schneider ,  Nikos P. Pitsianis ,  Grayson Morris ,  Edward A. Wolff ,  Patrick R. Marchand ,  Ricardo E. Rodriguez ,  Marco C. Jacobs

发明人： Gerald G. Pechanek ,  David Carl Strube ,  Edwin Frank Barry ,  Charles W. Kurak, JR. ,  Carl Donald Busboom ,  Dale Edward Schneider ,  Nikos P. Pitsianis ,  Grayson Morris ,  Edward A. Wolff ,  Patrick R. Marchand ,  Ricardo E. Rodriguez ,  Marco C. Jacobs

IPC分类号： G06F9/312 ,  G06F9/30

CPC分类号： G06F15/82 ,  G06F9/30145 ,  G06F11/263 ,  Y10S707/99943

摘要： Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized test cases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified.

摘要翻译： 这里描述了使用歧管阵列（ManArray）架构和指令语法的高成本有效和高效的实现的细节。 该方法的各个方面包括语法的规律性，指示集可以以数据库形式表示的相对容易程度，可以创建工具的就绪能力，即时生成自检代码和参数化测试用例。 可以很容易地映射参数化，并显着简化系统维护。

公开(公告)号：US20080301414A1

公开(公告)日：2008-12-04

申请号：US12187746

申请日：2008-08-07

申请人： Nikos P. Pitsianis ,  Gerald G. Pechanek ,  Ricardo E. Rodriguez

发明人： Nikos P. Pitsianis ,  Gerald G. Pechanek ,  Ricardo E. Rodriguez

IPC分类号： G06F9/302

CPC分类号： G06F15/82 ,  G06F9/30014 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3853 ,  G06F9/3885 ,  G06F15/8023 ,  G06F15/8038 ,  G06F17/142

摘要： Efficient computation of complex multiplication results and very efficient fast Fourier transforms (FFTs) are provided. A parallel array VLIW digital signal processor is employed along with specialized complex multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs are used allowing the complex multiplication pipeline hardware to be efficiently used. In addition, efficient techniques for supporting combined multiply accumulate operations are described.

摘要翻译： 提供了复数乘法结果和非常有效的快速傅里叶变换（FFT）的有效计算。 采用并行阵列VLIW数字信号处理器以及与计算重叠的处理元件之间的专用复数乘法指令和通信操作，以提供非常高的性能操作。 使用紧密封装的VLIW的循环的连续迭代，允许有效地使用复数乘法管线硬件。 此外，描述了用于支持组合乘法累加操作的有效技术。

公开(公告)号：US06839728B2

公开(公告)日：2005-01-04

申请号：US09337839

申请日：1999-06-22

申请人： Nikos P. Pitsianis ,  Gerald G. Pechanek ,  Ricardo E. Rodriguez

发明人： Nikos P. Pitsianis ,  Gerald G. Pechanek ,  Ricardo E. Rodriguez

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F15/16 ,  G06F15/173 ,  G06F15/80 ,  G06F17/14 ,  G06F17/16 ,  G06F15/00 ,  G06F7/52

CPC分类号： G06F15/82 ,  G06F9/30014 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3853 ,  G06F9/3885 ,  G06F15/8023 ,  G06F15/8038 ,  G06F17/142

摘要： Efficient computation of complex multiplication results and very efficient fast Fourier transforms (FFTs) are provided. A parallel array VLIW digital signal processor is employed along with specialized complex multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs are used allowing the complex multiplication pipeline hardware to be efficiently used. In addition, efficient techniques for supporting combined multiply accumulate operations are described.