Debug state machine and processor including the same
    11.
    发明授权
    Debug state machine and processor including the same 有权
    调试状态机和处理器相同

    公开(公告)号:US08566645B2

    公开(公告)日:2013-10-22

    申请号:US12958585

    申请日:2010-12-02

    IPC分类号: G06F11/00

    CPC分类号: G06F11/3636

    摘要: A processor or an integrated circuit chip including a debug state machine (DSM) that allows for programming complex triggering sequences for flexible and efficient debug visibility is disclosed. The DSM centralizes control of local debug functions such as trace start and stop, trace filtering, cross triggering between DSMs, clock stopping, triggering a system debug mode interrupt, flexible microcode interface, and the like. The DSM is configured to receive triggers from a processor core, other DSMs, a northbridge, other sockets, and the like and initiate a programmed action on a condition that a corresponding trigger or a sequence of triggers occurs.

    摘要翻译: 公开了一种处理器或集成电路芯片,其包括调试状态机(DSM),其允许编程复杂的触发序列以实现灵活和有效的调试可见性。 DSM集中控制本地调试功能,如跟踪启动和停止,跟踪过滤,DSM之间的交叉触发,时钟停止,触发系统调试模式中断,灵活的微代码接口等。 DSM被配置为从处理器核心,其他DSM,北桥,其他插座等接收触发,并且在相应的触发或触发序列发生的条件下启动编程的动作。