公开(公告)号：US20120144240A1

公开(公告)日：2012-06-07

申请号：US12958585

申请日：2010-12-02

申请人： Eric Rentschler ,  Steven J. Kommrusch ,  Scott P. Nixon

发明人： Eric Rentschler ,  Steven J. Kommrusch ,  Scott P. Nixon

IPC分类号： G06F11/07

CPC分类号： G06F11/3636

摘要： A processor or an integrated circuit chip including a debug state machine (DSM) that allows for programming complex triggering sequences for flexible and efficient debug visibility is disclosed. The DSM centralizes control of local debug functions such as trace start and stop, trace filtering, cross triggering between DSMs, clock stopping, triggering a system debug mode interrupt, flexible microcode interface, and the like. The DSM is configured to receive triggers from a processor core, other DSMs, a northbridge, other sockets, and the like and initiate a programmed action on a condition that a corresponding trigger or a sequence of triggers occurs.

摘要翻译： 公开了一种处理器或集成电路芯片，其包括调试状态机（DSM），其允许编程复杂的触发序列以实现灵活和有效的调试可见性。 DSM集中控制本地调试功能，如跟踪启动和停止，跟踪过滤，DSM之间的交叉触发，时钟停止，触发系统调试模式中断，灵活的微代码接口等。 DSM被配置为从处理器核心，其他DSM，北桥，其他插座等接收触发，并且在相应的触发或触发序列发生的条件下启动编程的动作。

公开(公告)号：US20050028069A1

公开(公告)日：2005-02-03

申请号：US10632199

申请日：2003-07-31

申请人： Larry Thayer ,  Eric Rentschler ,  Michael Tayler

发明人： Larry Thayer ,  Eric Rentschler ,  Michael Tayler

IPC分类号： G06F12/16 ,  G06F3/06 ,  G11C29/00

CPC分类号： G06F11/1076

摘要： The present invention is broadly directed to a memory system comprising a a host integrated circuit component, at least two data memories, at least one parity memory for storing parity information corresponding to data stored in a corresponding address space of the data memories, and at least two controller integrated circuits. Each controller integrated circuit (IC) comprises memory control logic configurable to control communications between the controller IC and data memories directly connected to the controller IC, parity logic configurable to compute parity information for data communicated to or from the data memories, logic configurable to communicate the parity information to or from a companion IC, and logic configurable to communicated data to or from a companion IC.

摘要翻译： 本发明广泛地涉及包括主机集成电路部件，至少两个数据存储器，至少一个奇偶校验存储器的存储器系统，用于存储对应于存储在数据存储器的相应地址空间中的数据的奇偶校验信息，以及至少两个 控制器集成电路。 每个控制器集成电路（IC）包括可配置为控制控制器IC与直接连接到控制器IC的数据存储器之间的通信的存储器控​​制逻辑，可配置为计算与数据存储器通信或从数据存储器传送的数据的奇偶校验信息的奇偶校验逻辑， 到或来自配对IC的奇偶校验信息，以及逻辑可配置为将数据传送到或来自配套IC。

公开(公告)号：US20130024829A1

公开(公告)日：2013-01-24

申请号：US13184982

申请日：2011-07-18

申请人： Benjamin Tsien ,  Kiran Bondalapati ,  Hao Huang ,  William A. Hughes ,  Eric Rentschler ,  Jeremy Schreiber ,  Aaron J. Grenat

发明人： Benjamin Tsien ,  Kiran Bondalapati ,  Hao Huang ,  William A. Hughes ,  Eric Rentschler ,  Jeremy Schreiber ,  Aaron J. Grenat

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G01R31/31705 ,  G06F2217/78

摘要： Described are a circuit and a method of analyzing and correcting a fault occurring in operation of the circuit during a power gating sequence. The method includes executing a modification of the power gating sequence that includes maintaining operation of a trace capture buffer (TCB); recording, in the TCB, events occurring during the executing; and correcting the fault based on analysis of the events recorded in the TCB. The circuit includes a plurality of components including a TCB, and a switch configured to maintain power to the TCB in a first state and turn off power to the TCB in a second state.

摘要翻译： 描述了在电源门控序列期间分析和校正在电路工作中发生的故障的电路和方法。 该方法包括执行包括维持跟踪捕获缓冲器（TCB）的操作的电源门控序列的修改; 在TCB中记录执行期间发生的事件; 并根据对TCB记录事件的分析来纠正故障。 该电路包括多个包括TCB的部件和被配置为在第一状态下保持对TCB的电源并且在第二状态下关闭到TCB的电源的开关。

公开(公告)号：US20050027891A1

公开(公告)日：2005-02-03

申请号：US10630460

申请日：2003-07-30

申请人： Darel Emmot ,  Eric Rentschler ,  Michael Tayler

发明人： Darel Emmot ,  Eric Rentschler ,  Michael Tayler

IPC分类号： G06F13/14 ,  G06F13/40 ,  G06F15/16

CPC分类号： G06F13/4027

摘要： The present invention is broadly directed to a integrated circuit component with a scalable architecture. In one embodiment, an integrated circuit component is provided comprising logic capable of being configured to interface with a first portion of a system bus, and logic capable of being configured to interface with a companion integrated circuit and to receive information that is communicated from the companion integrated circuit, which information was communicated to the companion integrated circuit via a second portion of the system bus.

摘要翻译： 本发明广泛涉及具有可扩展架构的集成电路部件。 在一个实施例中，提供集成电路组件，其包括能够被配置为与系统总线的第一部分进行接口的逻辑，以及能够被配置为与配套集成电路接口并且接收从伴侣传送的信息的逻辑 集成电路，该信息经由系统总线的第二部分传送到伴随的集成电路。

公开(公告)号：US08566645B2

公开(公告)日：2013-10-22

申请号：US12958585

申请日：2010-12-02

申请人： Eric Rentschler ,  Steven J. Kommrusch ,  Scott P. Nixon

发明人： Eric Rentschler ,  Steven J. Kommrusch ,  Scott P. Nixon

IPC分类号： G06F11/00

CPC分类号： G06F11/3636

摘要： A processor or an integrated circuit chip including a debug state machine (DSM) that allows for programming complex triggering sequences for flexible and efficient debug visibility is disclosed. The DSM centralizes control of local debug functions such as trace start and stop, trace filtering, cross triggering between DSMs, clock stopping, triggering a system debug mode interrupt, flexible microcode interface, and the like. The DSM is configured to receive triggers from a processor core, other DSMs, a northbridge, other sockets, and the like and initiate a programmed action on a condition that a corresponding trigger or a sequence of triggers occurs.

摘要翻译： 公开了一种处理器或集成电路芯片，其包括调试状态机（DSM），其允许编程复杂的触发序列以实现灵活和有效的调试可见性。 DSM集中控制本地调试功能，如跟踪启动和停止，跟踪过滤，DSM之间的交叉触发，时钟停止，触发系统调试模式中断，灵活的微代码接口等。 DSM被配置为从处理器核心，其他DSM，北桥，其他插座等接收触发，并且在相应的触发或触发序列发生的条件下启动编程的动作。

公开(公告)号：US5920326A

公开(公告)日：1999-07-06

申请号：US865903

申请日：1997-05-30

申请人： Eric Rentschler ,  Alan S. Krech, Jr. ,  Kendall F Tidwell

发明人： Eric Rentschler ,  Alan S. Krech, Jr. ,  Kendall F Tidwell

IPC分类号： G06T1/60 ,  G06F15/16

CPC分类号： G06T1/60

摘要： A computer graphics system for rendering graphics primitives based upon primitive data received from a host computer through a graphics interface. The primitive data may include vertex state and property state values. The computer graphics system includes a plurality of geometry accelerators configured to process the primitive data to render graphics primitives. The graphics primitives are rendered from one or more vertex states in accordance with the property states currently maintained in the rendering geometry accelerator. A distributor divides the primitive data into chunks of primitive data and distributes each of the primitive data chunks to a current geometry accelerator recipient. In one aspect of the invention, the distributor includes a state controller interposed between the host computer and said plurality of geometry accelerators. The state controller is configured to store and resend selected primitive data to the plurality of geometry accelerators based upon whether the one or more vertices of a graphics primitive are contained in more than one of the chunks of primitive data. A driver, based upon the occurrence of function calls that cause certain dependent property states to have values determined by the value assigned to a determining property state, controls the state controller to provide values of the determining property state to the geometry accelerators for values of said deponent property states.

摘要翻译： 一种用于基于通过图形接口从主计算机接收的原始数据来渲染图形基元的计算机图形系统。 原始数据可以包括顶点状态和属性状态值。 计算机图形系统包括被配置为处理原始数据以渲染图形基元的多个几何加速器。 图形基元根据当前在渲染几何加速器中保持的属性状态从一个或多个顶点状态渲染。 分销商将原始数据划分成原始数据块，并将每个原始数据块分配给当前的几何加速器接收方。 在本发明的一个方面，分配器包括置于主计算机和所述多个几何加速器之间的状态控制器。 状态控制器被配置为基于图形基元的一个或多个顶点是否包含在原始数据块中的多于一个的块中，将所选择的原始数据存储并重新发送到多个几何加速器。 驱动程序基于发生使得某些依赖属性状态具有由分配给确定属性状态的值确定的值的函数调用，控制状态控制器为所述几何加速器的值提供确定属性状态的值 权力财产状态。

公开(公告)号：US20050238127A1

公开(公告)日：2005-10-27

申请号：US10830375

申请日：2004-04-22

申请人： Samuel Naffziger ,  Eric Rentschler

发明人： Samuel Naffziger ,  Eric Rentschler

IPC分类号： H04J3/06 ,  H04L7/06

CPC分类号： H04J3/0682 ,  H04L7/0033

摘要： Systems, methods, and other embodiments associated with synchronizing link delay is provided. In one example system, a system for synchronizing signal communication between a first electronic component and a second electronic component connected by one or more serial communication links comprises an offset logic configured to apply a selected offset to signal transmissions to cause a unidirectional delay between the first and the second electronic components to be synchronized for both directions of signal transmissions. A synchronization logic is configured to determine the uni-directional delay for signal transmissions between the first and second electronic components and configured to control the offset logic to apply the selected offset.

摘要翻译： 提供了与同步链路延迟相关联的系统，方法和其他实施例。 在一个示例性系统中，用于使第一电子部件与由一个或多个串行通信链路连接的第二电子部件之间的信号通信同步的系统包括偏移逻辑，该偏移逻辑被配置为将所选择的偏移应用于信号传输，以引起第一 以及将信号传输的两个方向同步的第二电子部件。 同步逻辑被配置为确定第一和第二电子部件之间的信号传输的单向延迟，并且被配置为控制偏移逻辑以应用所选择的偏移。

公开(公告)号：US08595563B2

公开(公告)日：2013-11-26

申请号：US13184982

申请日：2011-07-18

申请人： Benjamin Tsien ,  Kiran Bondalapati ,  Hao Huang ,  William A. Hughes ,  Eric Rentschler ,  Jeremy Schreiber ,  Aaron J. Grenat

发明人： Benjamin Tsien ,  Kiran Bondalapati ,  Hao Huang ,  William A. Hughes ,  Eric Rentschler ,  Jeremy Schreiber ,  Aaron J. Grenat

IPC分类号： G06F11/00

CPC分类号： G06F17/505 ,  G01R31/31705 ,  G06F2217/78

摘要： Described are a circuit and a method of analyzing and correcting a fault occurring in operation of the circuit during a power gating sequence. The method includes executing a modification of the power gating sequence that includes maintaining operation of a trace capture buffer (TCB); recording, in the TCB, events occurring during the executing; and correcting the fault based on analysis of the events recorded in the TCB. The circuit includes a plurality of components including a TCB, and a switch configured to maintain power to the TCB in a first state and turn off power to the TCB in a second state.

摘要翻译： 描述了在电源门控序列期间分析和校正在电路工作中发生的故障的电路和方法。 该方法包括执行包括维持跟踪捕获缓冲器（TCB）的操作的电源门控序列的修改; 在TCB中记录执行期间发生的事件; 并根据对TCB记录事件的分析来纠正故障。 该电路包括多个包括TCB的部件和被配置为在第一状态下保持对TCB的电源并且在第二状态下关闭到TCB的电源的开关。

公开(公告)号：US20050240698A1

公开(公告)日：2005-10-27

申请号：US10830367

申请日：2004-04-22

申请人： Eric Rentschler ,  Samuel Naffziger

发明人： Eric Rentschler ,  Samuel Naffziger

IPC分类号： G01R31/317 ,  G06F13/372

CPC分类号： G01R31/31704 ,  G01R31/31705 ,  G01R31/31717 ,  G01R31/31725

摘要： Systems, methods, and other embodiments associated with a repeatable communication system are disclosed. One example system for receiving signals from an electronic component over a plurality of point-to-point communication links comprises a repeatability logic operably connected to each of the plurality of point-to-point communication links and configured to apply a delay offset to the signals received to compensate for frequency changes in signal transmissions over the plurality of point-to-point communication links.

摘要翻译： 公开了与可重复通信系统相关联的系统，方法和其他实施例。 用于通过多个点对点通信链路从电子部件接收信号的一个示例系统包括可操作地连接到多个点对点通信链路中的每一个的重复性逻辑，并且被配置为对信号应用延迟偏移 被接收以补偿在多个点对点通信链路上的信号传输中的频率变化。

公开(公告)号：US20050071554A1

公开(公告)日：2005-03-31

申请号：US10674262

申请日：2003-09-29

申请人： Larry Thayer ,  Eric Rentschler ,  Michael Tayler

发明人： Larry Thayer ,  Eric Rentschler ,  Michael Tayler

IPC分类号： G06F12/16 ,  G06F3/06 ,  G06F12/00

CPC分类号： G06F11/1076

摘要： Embodiments of the present invention are broadly directed to a memory system. In one embodiment, a first data memory is coupled to a first memory controller and a second data memory is coupled to a second memory controller. A parity memory is coupled to a parity controller, the parity controller being directly coupled to both the first memory controller and the second memory controller. Parity data control logic is configured to store and retrieve parity information associated with data stored in both the first data memory and the second data memory, the parity data control logic configured to interleave within the parity memory parity data associated with data stored in the first data memory with parity data associated with data stored in the second data memory.

摘要翻译： 本发明的实施例广泛地涉及存储器系统。 在一个实施例中，第一数据存储器耦合到第一存储器控制器，并且第二数据存储器耦合到第二存储器控制器。 奇偶校验存储器耦合到奇偶校验控制器，奇偶校验控制器直接耦合到第一存储器控制器和第二存储器控制器两者。 奇偶校验数据控制逻辑被配置为存储和检索与存储在第一数据存储器和第二数据存储器中的数据相关联的奇偶校验信息，奇偶校验数据控制逻辑被配置为在与存储在第一数据中的数据相关联的奇偶校验存储器奇偶校验数据内交错 具有与存储在第二数据存储器中的数据相关联的奇偶校验数据的存储器。