公开(公告)号：US07920036B2

公开(公告)日：2011-04-05

申请号：US12203003

申请日：2008-09-02

Applicant: Andreia Cathelin ,  Stephane Razafimandimby ,  Andreas Kaiser

Inventor： Andreia Cathelin ,  Stephane Razafimandimby ,  Andreas Kaiser

IPC: H03H9/54 ,  H03H3/04

CPC classification number: H03H9/0095 ,  H03H9/542 ,  H03J7/02

Abstract: A lattice tunable filtering circuit includes a first input and a second input, and a first output and a second output. The circuit includes two series branches and two parallel branches. The first and second series branches include a Tunable Resonator Component (TRC) which presents a first series resonance frequency whereas the third and fourth parallel branches present a second series resonance frequency which has a value being lower than that of the first series resonance frequency. The first and second series resonance frequencies are tunable by one analog control quantity. The filtering circuit further includes a feedback control loop for the control of the analog quantity, which feedback is based on a criterion of equality between the modulus of impedances Zs and Zp.

Abstract translation: 晶格可调滤波电路包括第一输入和第二输入，以及第一输出和第二输出。 该电路包括两个串联分支和两个并行分支。 第一和第二串联分支包括提供第一串联谐振频率的可调谐谐振器分量（TRC），而第三和第四并联分支呈现第二串联谐振频率，其具有低于第一串联谐振频率的值。 第一和第二串联谐振频率可通过一个模拟量控制量来调节。 滤波电路还包括用于控制模拟量的反馈控制回路，该反馈基于阻抗模Zs和Zp之间相等的标准。

公开(公告)号：US20090072925A1

公开(公告)日：2009-03-19

申请号：US12203003

申请日：2008-09-02

Applicant: Andreia Cathelin ,  Stephane Razafimandimby ,  Andreas Kaiser

Inventor： Andreia Cathelin ,  Stephane Razafimandimby ,  Andreas Kaiser

IPC: H03H9/58

CPC classification number: H03H9/0095 ,  H03H9/542 ,  H03J7/02

Abstract: A lattice tunable filtering circuit includes a first input and a second input, and a first output and a second output. The circuit includes two series branches and two parallel branches. The first and second series branches include a Tunable Resonator Component (TRC) which presents a first series resonance frequency whereas the third and fourth parallel branches present a second series resonance frequency which has a value being lower than that of the first series resonance frequency. The first and second series resonance frequencies are tunable by one analog control quantity. The filtering circuit further includes a feedback control loop for the control of the analog quantity, which feedback is based on a criterion of equality between the modulus of impedances Zs and Zp.

Abstract translation: 晶格可调滤波电路包括第一输入和第二输入，以及第一输出和第二输出。 该电路包括两个串联分支和两个并行分支。 第一和第二串联分支包括提供第一串联谐振频率的可调谐谐振器分量（TRC），而第三和第四并联分支呈现第二串联谐振频率，其具有低于第一串联谐振频率的值。 第一和第二串联谐振频率可通过一个模拟量控制量来调节。 滤波电路还包括用于控制模拟量的反馈控制回路，该反馈基于阻抗模Zs和Zp之间相等的标准。

公开(公告)号：US07423502B2

公开(公告)日：2008-09-09

申请号：US11024950

申请日：2004-12-29

Applicant: Stephane Razafimandimby ,  Didier Belot ,  Jean-François Carpentier ,  Andreia Cathelin

Inventor： Stephane Razafimandimby ,  Didier Belot ,  Jean-François Carpentier ,  Andreia Cathelin

IPC: H03H9/00 ,  H03H9/56

CPC classification number: H03H11/486 ,  H03H11/50 ,  H03H2009/02204

Abstract: An electronic circuit comprises a resonator meant to be integrated into a semiconductor product including a resonator having first and second resonant frequencies. The electronic circuit comprises: a first inductive partner element for canceling out said second resonant frequency, said partner element having a quality coefficient QI (f) having a first value in a predetermined frequency band and a second value outside said frequency band; a second capacitive partner element for adjusting tuning of said resonator to said first frequency.

Abstract translation: 一种电子电路包括一个谐振器，该谐振器被集成到包括具有第一和第二谐振频率的谐振器的半导体产品中。 电子电路包括：用于消除所述第二谐振频率的第一电感对象元件，所述伙伴元件具有在预定频带中具有第一值的质量系数QI（f）和在所述频带外的第二值; 第二电容伙伴元件，用于将所述谐振器的调谐调节到所述第一频率。

公开(公告)号：US20080088390A1

公开(公告)日：2008-04-17

申请号：US11840140

申请日：2007-08-16

Applicant: Andreia Cathelin ,  Stephane Razafimandimby ,  Cyrille Tilhac

Inventor： Andreia Cathelin ,  Stephane Razafimandimby ,  Cyrille Tilhac

IPC: H03H9/00

CPC classification number: H03B5/326 ,  H03B5/366 ,  H03H11/481

Abstract: A negative capacity circuit comprising: a first branch connected between a first reference voltage and a second voltage reference, said first branch comprising, in series, a first biasing resistor, a first diode, a collector-emitter junction of a first bipolar transistor and a first current source; a second branch connected between said first reference voltage (Vdd) and said second reference voltage, said second branch comprising, in series, a second biasing resistor, a second diode, a collector-emitter junction of a second bipolar transistor and a second current source, said first transistor having a base terminal which is coupled to the collector terminal of said second transistor and to one input, and said second transistor having a base terminal which is coupled to the collector terminal of said first transistor and to another input; a capacitor connected between the emitter terminal of said first bipolar transistor and the emitter terminal of said second bipolar transistor; a linearization resistor which is coupled in parallel between the two emitter terminals of said first and said second bipolar transistors.

Abstract translation: 一种负容量电路，包括：连接在第一参考电压和第二参考电压之间的第一分支，所述第一分支串联包括第一偏压电阻器，第一二极管，第一双极晶体管的集电极 - 发射极结和 第一电流源; 连接在所述第一参考电压（Vdd）和所述第二参考电压之间的第二分支，所述第二分支串联包括第二偏置电阻器，第二二极管，第二双极晶体管的集电极 - 发射极结和第二电流源 所述第一晶体管具有耦合到所述第二晶体管的集电极端子的基极端子和一个输入端，所述第二晶体管具有耦合到所述第一晶体管的集电极端子和另一输入端的基极端子; 连接在所述第一双极晶体管的发射极端子和所述第二双极晶体管的发射极端子之间的电容器; 线性化电阻器并联在所述第一和所述第二双极晶体管的两个发射极端子之间。