公开(公告)号：US07692497B2

公开(公告)日：2010-04-06

申请号：US11707778

申请日：2007-02-12

申请人： Jianbin Hao ,  Ning Zhu ,  Yanjing Ke

发明人： Jianbin Hao ,  Ning Zhu ,  Yanjing Ke

IPC分类号： H03L7/00

CPC分类号： H03L7/10 ,  H03L7/0891 ,  H03L7/099

摘要： The present invention provides a method and mechanism for adapting a single phase-locked loop (PLL) for a wider range of frequencies than has been possible with prior art solutions. An analog comparator circuit that senses the output of a charge pump and provides a signal to a digital control circuit to choose a suitable load circuit for the PLL voltage controlled oscillator (VCO). The analog comparator with the digital control circuit changes the VCO loads to select the best VCO range to achieve the incoming signal frequency lock. A single PLL with the VCO load selection method disclosed, with use of built-in hysteresis, in addition to the phase and frequency feedback of the prior art, allows multiple overlapping frequency ranges to be covered in a stable fashion. This enables frequency locking of the PLL over a wide range of frequencies with a small die size and low power consumption.

摘要翻译： 本发明提供了一种用于适应比现有技术解决方案可能的更宽范围频率的单个锁相环（PLL）的方法和机制。 模拟比较器电路，用于检测电荷泵的输出，并向数字控制电路提供信号，为PLL压控振荡器（VCO）选择合适的负载电路。 具有数字控制电路的模拟比较器改变VCO负载，以选择最佳VCO范围来实现输入信号频率锁定。 除了现有技术的相位和频率反馈之外，利用内置迟滞公开的具有VCO负载选择方法的单个PLL允许以稳定的方式覆盖多个重叠的频率范围。 这使得PLL能够在较小的芯片尺寸和低功耗的宽范围的频率上锁定PLL。