公开(公告)号：US20190005240A1

公开(公告)日：2019-01-03

申请号：US15635614

申请日：2017-06-28

Applicant: ARM Limited

Inventor： Guillaume SCHON ,  Frederic Jean Denis ARSANTO ,  Jocelyn François Orion JAUBERT ,  Carlo Dario FANARA

IPC: G06F21/56 ,  G06F3/06

CPC classification number: G06F21/566 ,  G06F3/0622 ,  G06F3/0637 ,  G06F3/0679 ,  G06F21/577 ,  G06F21/6218 ,  G06F21/78 ,  G06F2221/034

Abstract: An apparatus has a number of data holding elements for holding data values which are reset to a reset value in response to a transition of a signal at a reset signal input of the data holding element from a first value to a second value. A reset tree is provided to distribute a reset signal received at root node of the reset tree to the reset signal inputs of the data holding elements. At least one reset attack detection element is provided, with its reset signal input coupled to a given node of the reset tree, to assert an error signal when its reset signal input transitions from the first value to a second value. Reset error clearing circuitry triggers clearing of the error signal, when the reset signal at the root node of the reset tree transitions from the second value to the first value.

公开(公告)号：US20140289501A1

公开(公告)日：2014-09-25

申请号：US13847892

申请日：2013-03-20

Applicant: ARM Limited

Inventor： Guillaume SCHON ,  Cedric Denis Robert AIRAUD ,  Frederic Jean Denis ARSANTO ,  Luca SCALABRINO

IPC: G06F9/30

CPC classification number: G06F9/3017 ,  G06F9/30098 ,  G06F9/384 ,  G06F9/3857 ,  G06F9/3863

Abstract: Register renaming circuitry for a processing apparatus configured to process a stream of instructions from an instruction set specifying registers from an architectural set of registers. The apparatus including a physical set of registers configured to store data values being processed by the processing apparatus. Register renaming circuitry is configured to receive a stream of operations from an instruction decoder and to map registers that are to be written to by the stream of operations to physical registers within the physical set of registers that are currently available. The register renaming circuitry comprises register release circuitry configured to release the physical registers that have been mapped to the registers when a first set of conditions have been met, and to release the physical registers that have been mapped to the additional registers when a second set of conditions have been met.

Abstract translation: 用于处理装置的注册重命名电路，被配置为处理来自指定集合的​​指令集的指令流，所述指令集指定来自架构的一组寄存器。 该装置包括被配置为存储由处理装置处理的数据值的寄存器的物理组。 寄存器重命名电路被配置为从指令解码器接收操作流，并将要由操作流写入的寄存器映射到当前可用的寄存器的物理组内的物理寄存器。 寄存器重命名电路包括寄存器释放电路，其被配置为当满足第一组条件时释放已经被映射到寄存器的物理寄存器，并且当第二组存储器被释放时已被映射到附加寄存器的物理寄存器 条件得到满足。