公开(公告)号：US20190018686A1

公开(公告)日：2019-01-17

申请号：US15651158

申请日：2017-07-17

Applicant: ARM LIMITED

Inventor： Jocelyn Francois Orion JAUBERT ,  Frederic Jean Denis ARSANTO ,  Guillaume SCHON ,  Carlo Dario FANARA

IPC: G06F9/38 ,  G06F9/30

Abstract: An apparatus comprising: a set of registers; and mapping circuitry to perform a mapping operation to map each of a set of register specifiers to a respective register from among the set of registers in dependence on a mapping function. The mapping function is dependent on a key value. In addition, the mapping for at least two register specifiers from among the set of register specifiers is dependent on the same key value.

公开(公告)号：US20140195787A1

公开(公告)日：2014-07-10

申请号：US13737153

申请日：2013-01-09

Applicant: ARM LIMITED

Inventor： Luca SCALABRINO ,  Melanie Emanuelle Lucie TEYSSIER ,  Cedric Denis Robert AIRAUD ,  Guillaume SCHON

IPC: G06F9/38

CPC classification number: G06F9/3842 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3885

Abstract: First processing circuitry processes at least part of a stream of program instructions. The first processing circuitry has registers for storing data and register renaming circuitry for mapping architectural register specifiers to physical register specifiers. A renaming data store stores renaming entries for identifying a register mapping between the architectural and physical register specifiers. At least some renaming entries have a count value indicating a number of speculation points occurring between generation of a previous count value and generation of the count value. The speculation points may for example be branch operation or load/store operations.

Abstract translation: 第一处理电路处理程序指令流的至少一部分。 第一处理电路具有用于存储数据和寄存器重命名电路的寄存器，用于将架构寄存器说明符映射到物理寄存器说明符。 重命名数据存储存储用于识别架构和物理寄存器说明符之间的寄存器映射的重命名条目。 至少一些重命名条目具有指示在生成先前计数值和生成计数值之间发生的推测点数的计数值。 推测点可以例如是分支操作或加载/存储操作。

公开(公告)号：US20190121967A1

公开(公告)日：2019-04-25

申请号：US15793186

申请日：2017-10-25

Applicant: ARM Limited

Inventor： Guillaume SCHON ,  Frederic Jean Denis ARSANTO ,  Carlo Dario FANARA ,  Jocelyn François Orion JAUBERT

IPC: G06F21/55 ,  G06F11/30 ,  G06F9/30

Abstract: Data processing circuitry comprises a set of two or more computational units to perform respective computational operations; an instruction decoder to decode successive data processing instructions and, for a given data processing instruction, to control one or more of the computational units to perform those computational operations required to execute the given data processing instruction; and control circuitry responsive to the given data processing instruction, to control one or more others of the computational units to perform further computational operations, other than the computational operations required to execute the given data processing instruction, during execution of the given data processing instruction.

公开(公告)号：US20190005240A1

公开(公告)日：2019-01-03

申请号：US15635614

申请日：2017-06-28

Applicant: ARM Limited

Inventor： Guillaume SCHON ,  Frederic Jean Denis ARSANTO ,  Jocelyn François Orion JAUBERT ,  Carlo Dario FANARA

IPC: G06F21/56 ,  G06F3/06

CPC classification number: G06F21/566 ,  G06F3/0622 ,  G06F3/0637 ,  G06F3/0679 ,  G06F21/577 ,  G06F21/6218 ,  G06F21/78 ,  G06F2221/034

Abstract: An apparatus has a number of data holding elements for holding data values which are reset to a reset value in response to a transition of a signal at a reset signal input of the data holding element from a first value to a second value. A reset tree is provided to distribute a reset signal received at root node of the reset tree to the reset signal inputs of the data holding elements. At least one reset attack detection element is provided, with its reset signal input coupled to a given node of the reset tree, to assert an error signal when its reset signal input transitions from the first value to a second value. Reset error clearing circuitry triggers clearing of the error signal, when the reset signal at the root node of the reset tree transitions from the second value to the first value.

公开(公告)号：US20140289501A1

公开(公告)日：2014-09-25

申请号：US13847892

申请日：2013-03-20

Applicant: ARM Limited

Inventor： Guillaume SCHON ,  Cedric Denis Robert AIRAUD ,  Frederic Jean Denis ARSANTO ,  Luca SCALABRINO

IPC: G06F9/30

CPC classification number: G06F9/3017 ,  G06F9/30098 ,  G06F9/384 ,  G06F9/3857 ,  G06F9/3863

Abstract: Register renaming circuitry for a processing apparatus configured to process a stream of instructions from an instruction set specifying registers from an architectural set of registers. The apparatus including a physical set of registers configured to store data values being processed by the processing apparatus. Register renaming circuitry is configured to receive a stream of operations from an instruction decoder and to map registers that are to be written to by the stream of operations to physical registers within the physical set of registers that are currently available. The register renaming circuitry comprises register release circuitry configured to release the physical registers that have been mapped to the registers when a first set of conditions have been met, and to release the physical registers that have been mapped to the additional registers when a second set of conditions have been met.

Abstract translation: 用于处理装置的注册重命名电路，被配置为处理来自指定集合的​​指令集的指令流，所述指令集指定来自架构的一组寄存器。 该装置包括被配置为存储由处理装置处理的数据值的寄存器的物理组。 寄存器重命名电路被配置为从指令解码器接收操作流，并将要由操作流写入的寄存器映射到当前可用的寄存器的物理组内的物理寄存器。 寄存器重命名电路包括寄存器释放电路，其被配置为当满足第一组条件时释放已经被映射到寄存器的物理寄存器，并且当第二组存储器被释放时已被映射到附加寄存器的物理寄存器 条件得到满足。

公开(公告)号：US20190004977A1

公开(公告)日：2019-01-03

申请号：US15638524

申请日：2017-06-30

Applicant: ARM LIMITED

Inventor： Carlo Dario FANARA ,  Frederic Jean Denis ARSANTO ,  Guillaume SCHON ,  Jocelyn Francois Orion JAUBERT

IPC: G06F12/14 ,  G06F9/44 ,  G06F9/24 ,  G06F1/24 ,  G06F9/30

Abstract: An apparatus has processing circuitry to perform data processing in one of two or more operating states associated with different levels of privilege. At least one operating state holding element holds a state indication indicating a current operating state of the processing circuitry. In response to a transition of a reset signal from a first value to a second value for triggering a reset of the processing circuitry, the at least one operating state holding element resets the state indication to indicate a default operating state other than a most privileged operating state of the two or more operating states.

公开(公告)号：US20140215189A1

公开(公告)日：2014-07-31

申请号：US13752621

申请日：2013-01-29

Applicant: ARM LIMITED

Inventor： Cedric Denis Robert AIRAUD ,  Luca SCALABRINO ,  Frederic Jean Denis ARSANTO ,  Guillaume SCHON ,  Frederic Claude Marie PIRY ,  Albin Pierick TONNERRE

IPC: G06F9/30

CPC classification number: G06F9/3836 ,  G06F9/30014 ,  G06F9/30196

Abstract: An apparatus and method includes execution circuitry including a wide operand execution unit configured to allow up to N bits of operand data to be processed during execution of a single instruction. Decoder circuitry decodes and generates, for each instruction, at least one control data block identifying an operation to be performed by the execution circuitry and at least two re-combineable control data blocks for the instruction. Issue queue control circuitry then allocates a slot in the issue queue for each of the at least two data blocks and up to M bits of associated operand data, and marks those allocated slots to identify that they contain re-combineable control data blocks. The issue queue control circuitry issues the combined block to said wide operand execution unit along with the operand data contained in each of the allocated slots for said at least two control data blocks.

Abstract translation: 一种装置和方法包括执行电路，其包括宽操作数执行单元，其被配置为允许在单个指令的执行期间处理最多N位的操作数数据。 解码器电路针对每个指令对至少一个控制数据块进行解码并生成至少一个控制数据块，该控制数据块标识由执行电路执行的操作和用于该指令的至少两个可重新组合的控制数据块。 发出队列控制电路然后为发送队列中的每个至少两个数据块和相关操作数数据的高达M位分配一个时隙，并标记这些分配的时隙以标识它们包含可重新组合的控制数据块。 所述问题队列控制电路与包含在所述至少两个控制数据块的所分配的时隙中的操作数数据一起向所述宽操作数执行单元发出组合块。