公开(公告)号：US20080183790A1

公开(公告)日：2008-07-31

申请号：US11938252

申请日：2007-11-09

Applicant: Alan N. Willson, Jr.

Inventor： Alan N. Willson, Jr.

IPC: G06F7/548

CPC classification number: G06F7/4818

Abstract: An apparatus and method for angle is disclosed to rotate a complex input by the angle θ to produce a rotated complex output signal. A memory storage device generates control information based on a coarse angle θM. A coarse rotation butterfly circuit uses the control information to rotate the complex input signal by the coarse angle θM to produce an intermediate complex number. The control information controls one or more multiplexers and/or adders in the coarse rotation butterfly circuit to information to rotate the complex input signal. The fine rotation butterfly circuit uses the control information to rotate the intermediate complex number by a fine angle θL to produce the complex output signal. The control information controls one or more multiplexers and/or adders in the fine rotation butterfly circuit to rotate the intermediate complex number.

Abstract translation: 公开了一种用于角度的装置和方法，以使复数输入旋转角度θ以产生旋转的复数输出信号。 存储器存储装置基于粗略角度θM生成控制信息。 粗略旋转蝶形电路使用控制信息使复数输入信号旋转粗角度θM以产生中间复数。 控制信息将粗略旋转蝶形电路中的一个或多个多路复用器和/或加法器控制为旋转复合输入信号的信息。 微旋转蝶形电路使用控制信息将中间复数旋转一个微小的角度θL来产生复数输出信号。 控制信息控制微旋转蝶形电路中的一个或多个多路复用器和/或加法器来旋转中间复数。

公开(公告)号：US07225217B2

公开(公告)日：2007-05-29

申请号：US10268602

申请日：2002-10-09

Applicant: Alan N. Willson, Jr. ,  Zhan Yu ,  Larry S. Wasserman

Inventor： Alan N. Willson, Jr. ,  Zhan Yu ,  Larry S. Wasserman

IPC: G06F7/52

CPC classification number: G06F7/5338

Abstract: An enhanced Booth-encoded adder-array multiplier where the low transition probability partial-products are generated and the adder array has been reorganized to reduce power dissipation when the Booth-encoded input has a large dynamic range. The architecture does not require extra circuits or routing overhead. Power dissipation is reduced by ordering the sequence of partial-product additions such that an increasing sequence of “transition probabilities” is encountered.

Abstract translation: 增强的布斯编码加法器阵列乘法器，其中生成低转移概率部分乘积，并且当布斯编码输入具有大的动态范围时，加法器阵列已被重组以减少功率耗散。 该架构不需要额外的电路或路由开销。 通过排序部分产品添加的顺序来减少功耗，使得遇到增加的“转移概率”序列。

公开(公告)号：US07203718B1

公开(公告)日：2007-04-10

申请号：US09698246

申请日：2000-10-30

Applicant: Dengwei Fu ,  Arthur Torosyan ,  Alan N. Willson, Jr.

Inventor： Dengwei Fu ,  Arthur Torosyan ,  Alan N. Willson, Jr.

IPC: G06F7/52

CPC classification number: G06F7/5446

Abstract: An angle rotator uses a coarse stage rotation and a fine stage rotation to rotate an input complex signal in the complex plane according to an angle θ. The coarse stage rotation includes a memory device storing pre-computed cosine θM and sine θM values for fast retrieval, where θM is a radian angle that corresponds to a most significant word (MSW) of the input angle θ. The fine stage rotation uses one or more error values that compensate for approximations and quantization errors associated with the coarse stage rotation. The rotator consolidates operations into a small number of reduced-size multipliers, enabling efficient multiplier implementations such as Booth encoding, yielding a smaller and faster overall circuit.

Abstract translation: 角度旋转器使用粗级旋转和精细级旋转来根据角度θ旋转复平面中的输入复信号。 粗级旋转包括用于快速检索的存储预先计算的余弦θ和正弦值的存储器件，其中θ是M 弧度角对应于输入角θ的最高有效字（MSW）。 精细级旋转使用补偿与粗级旋转相关联的近似和量化误差的一个或多个误差值。 旋转器将操作整合到少量的小尺寸乘法器中，实现高效的乘法器实现，如布斯编码，产生更小更快的总体电路。

公开(公告)号：US5479363A

公开(公告)日：1995-12-26

申请号：US055975

申请日：1993-04-30

Applicant: Alan N. Willson, Jr. ,  Kei Y. Khoo ,  Alan Kwentus

Inventor： Alan N. Willson, Jr. ,  Kei Y. Khoo ,  Alan Kwentus

IPC: H03H17/02 ,  G06F15/31

CPC classification number: H03H17/0294

Abstract: A novel switchable unit-delay has been developed for the efficient implementation of programmable digital finite impulse response filters and correlators. A p-tap consisting of this novel switchable unit-delay and a two-non-zero-digit partial product generator and adder have been implemented. The combination of several p-taps, made possible by the switchable unit-delay, allows for the efficient implementation of coefficients with more than two non-zero digits. In a straightforward implementation of a programmable finite impulse response filter, many tap "multipliers" would significantly waste valuable computational resources since all filter taps would need to accommodate "difficult" coefficient values (i.e., many non-zero digits), while for any specific transfer function, most filter taps would not require such extreme capabilities. The switchable unit-delay not only allows the programing of the number of taps and the specific tap-coefficient values, it provides the capability for programing the optimal allocation of hardware resources to each filter tap.

Abstract translation: 已经开发了一种新颖的可切换单位延迟，用于有效实现可编程数字有限脉冲响应滤波器和相关器。 已经实现了由这种新颖的可切换单位延迟组成的p抽头和二非零位部分乘积发生器和加法器。 通过可切换单位延迟实现的几个p-tap的组合允许有效实现具有两个以上非零数字的系数。 在可编程有限脉冲响应滤波器的简单实现中，许多抽头“乘法器”将显着浪费有价值的计算资源，因为所有滤波器抽头将需要适应“困难”系数值（即，许多非零数字），而对于任何特定的 传输功能，大多数滤镜不需要这样的极限能力。 可切换单元延迟不仅允许对抽头数量和特定抽头系数值进行编程，还提供了将硬件资源的最佳分配编程到每个过滤器抽头的能力。