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公开(公告)号：US06772181B1
公开(公告)日：2004-08-03
申请号：US09699088
申请日：2000-10-30
Applicant: Dengwei Fu , Alan N. Willson, Jr.
Inventor： Dengwei Fu , Alan N. Willson, Jr.
IPC: G06F1717
CPC classification number: G06F17/17 , H03H17/0628
Abstract: A trigonometric interpolator interpolates between two data samples at an offset &mgr;, where the two data samples are part of a set of N data samples. The trigonometric interpolator fits a trigonometric polynomial to the N data samples and evaluates the trigonometric polynomial at the offset &mgr;. The trigonometric inteprolator can be utilized for data rate changing and to correct mismatches between received samples and transmitted symbols. Simulations demonstrate that the trigonometric interpolater attains better performance than “conventional” interpolators, while simultaneously reducing the required hardware. In embodiments, the filter response of the trigonometric interpolator can be modified to achieve an arbitrary frequency response in order to enhance the interpolator performance. More specifically, the frequency response of the interpolator can be shaped to effectively correspond with the frequency response of the input data samples and the offset &mgr;. Using this optimization technique, the overall interpolation error is reduced. As for the implementation, the optimal interpolator does not require additional hardware when a lookup table is used for sine and cosine values. When high precision, high speed and a small table are desired, the trigonometric interpolator can be implemented using an angle-rotation processor that is also described here.
Abstract translation: 三角插值器在偏移量mu处的两个数据样本之间插值，其中两个数据样本是一组N个数据样本的一部分。 三角内插器将三角多项式拟合到N个数据样本，并评估偏移量mu处的三角多项式。 三角内向推进器可用于数据速率变化，并纠正接收到的采样和发射符号之间的不匹配。 仿真表明，三角插值仪比“传统”插值器获得更好的性能，同时减少了所需的硬件。 在实施例中，可以修改三角插值器的滤波器响应以实现任意频率响应，以便增强内插器性能。 更具体地，内插器的频率响应可以被成形为有效地对应于输入数据样本和偏移量mu的频率响应。 使用这种优化技术，整体插值误差降低。 对于实现，当查找表用于正弦和余弦值时，最佳内插器不需要额外的硬件。 当需要高精度，高速度和小表时，可以使用这里也描述的角度旋转处理器来实现三角插值器。
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公开(公告)号：US06553397B2
公开(公告)日：2003-04-22
申请号：US09912177
申请日：2001-07-24
Applicant: Alan N. Willson, Jr. , Larry S. Wasserman
Inventor： Alan N. Willson, Jr. , Larry S. Wasserman
IPC: G06F1710
CPC classification number: H03H17/06 , H03H17/0223 , H03H17/0275 , H03H17/0657 , H03H21/0012 , H03H2218/12
Abstract: A method, apparatus, article of manufacture, and a memory structure for low power digital processing is disclosed. Tap values are modified by one or more factors to increase computational efficiency and a bias factor used to compensate for changes in the processor output response that result from the modification of the tap values.
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公开(公告)号：US08131793B2
公开(公告)日：2012-03-06
申请号：US11938252
申请日：2007-11-09
Applicant: Alan N. Willson, Jr.
Inventor： Alan N. Willson, Jr.
IPC: G06F7/38
CPC classification number: G06F7/4818
Abstract: An apparatus and method for angle is disclosed to rotate a complex input by the angle θ to produce a rotated complex output signal. A memory storage device generates control information based on a coarse angle θM. A coarse rotation butterfly circuit uses the control information to rotate the complex input signal by the coarse angle θM to produce an intermediate complex number. The control information controls one or more multiplexers and/or adders in the coarse rotation butterfly circuit to information to rotate the complex input signal. The fine rotation butterfly circuit uses the control information to rotate the intermediate complex number by a fine angle θL to produce the complex output signal. The control information controls one or more multiplexers and/or adders in the fine rotation butterfly circuit to rotate the intermediate complex number.
Abstract translation: 公开了一种用于角度的装置和方法，以使复数输入旋转角度和角度; 以产生旋转的复数输出信号。 存储器存储装置根据粗略角度生成控制信息; M。 粗旋转蝶形电路使用控制信息使复数输入信号以粗角度＆M; M旋转以产生中间复数。 控制信息将粗略旋转蝶形电路中的一个或多个多路复用器和/或加法器控制为旋转复数输入信号的信息。 精细旋转蝶形电路使用控制信息将中间复数旋转一个微小的角度，以产生复数输出信号。 控制信息控制微旋转蝶形电路中的一个或多个多路复用器和/或加法器来旋转中间复数。
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公开(公告)号：US06874006B1
公开(公告)日：2005-03-29
申请号：US09698249
申请日：2000-10-30
Applicant: Dengwei Fu , Alan N. Willson, Jr.
Inventor： Dengwei Fu , Alan N. Willson, Jr.
CPC classification number: H04L27/22
Abstract: A rectangular-to-polar-converter receives a complex input signal (having X0 and Y0 components) and determines an angle φ that represents the position of the complex signal in the complex plane. The rectangular-to polar-converter determines a coarse angle φ1 and a fine angle φ2, where φ=φ1+φ2. The coarse angle φ1 is obtained using a small arctangent table and a reciprocal table. These tables provide just enough precision such that the remaining fine angle φ2 is small enough to approximately equal its tangent value. Therefore the fine angle φ2 can be obtained without a look-up table, and the fine angle computations are consolidated into a few small multipliers, given a precision requirement. Applications of the rectangular-to-polar converter include symbol and carrier synchronization, including symbol synchronization for bursty transmissions of packet data systems. Other applications include any application requiring the rectangular-to-polar conversion of a complex input signal.
Abstract translation: 矩形到极性转换器接收复数输入信号（具有X0和Y0分量）并且确定表示复平面中的复信号的位置的角度phi。 矩形到极化转换器确定粗角度phi1和精细角度phi2，其中phi = phi1 + phi2。 使用小的反正切表和倒数表获得粗角度phi1。 这些表提供足够的精度，使得剩余的细角度phi2足够小以近似等于其切线值。 因此，在没有查找表的情况下可以获得细角度phi2，并且在精度要求下，将精细角度计算合并到几个小乘数中。 矩形到极化转换器的应用包括符号和载波同步，包括分组数据系统的突发传输的符号同步。 其他应用包括需要复合输入信号的矩形到极化转换的任何应用。
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公开(公告)号：US06308190B1
公开(公告)日：2001-10-23
申请号：US09211357
申请日：1998-12-15
Applicant: Alan N. Willson, Jr. , Larry S. Wasserman
Inventor： Alan N. Willson, Jr. , Larry S. Wasserman
IPC: G06F1710
CPC classification number: H03H17/06 , H03H17/0223 , H03H17/0275 , H03H17/0657 , H03H21/0012 , H03H2218/12
Abstract: A method, apparatus, article of manufacture, and a memory structure for low power digital filtering. The method comprises the steps of successively delaying each of the input values {x0,x1, . . . ,xN−1} to create tap values {t0,t1, . . . ,tN−1}, multiplying each of the tap values {t0,t1, . . . ,tN−1} by A•{h0,h1, . . . ,hN−1} to produce {At0h0,At1h1, . . . ,AtN−1hN−1}wherein values {h0,h1, . . . ,hN−1} are weight values selected to achieve a desired filter response and A is a factor selected to improve computational efficiency in filtering the input data stream, summing the values {At0h0,At1h1, . . . ,AtN−1hN−1} to produce ∑ k = 0 N - 1 At k h k , biasing the summed values {At0h0,At1h1, . . . ,AtN−1hN−1} to compensate for the modified filter tap values and to produce a digital filter output. The article of manufacture comprises means for performing the above method steps. The apparatus comprises an interconnected series of k stages wherein k={1,2, . . . ,N−1}. Each of the stages comprises a delay element Zk−1 having a delay element input and a delay element output, a weighting element having a weighting element input and a weighting element output, wherein a gain of the weighting element is selected to be a product of a gain hk required to achieve a desired digital filter response, and a factor A selected to improve computational efficiency, and a summation element having a first summation element input, a second summation element input, and a summation element output. A bias summation element is coupled between the leading gain element and the first stage summation element, for adding a bias to compensate for the factored weighting element gains.
Abstract translation: 一种用于低功率数字滤波的方法，装置，制品和存储结构。 该方法包括以下步骤：将输入值{x0，x1，...， 。 。 ，xN-1}来创建抽头值{t0，t1，...。 。 。 ，tN-1}，将每个抽头值{t0，t1，...， 。 。 ，tN-1}由A. {h0，h1，... 。 。 ，hN-1}以产生{At0h0，At1h1，... 。 。 ，AtN-1hN-1}，其中值{h0，h1，... 。 。 ，hN-1}是选择以获得期望的滤波器响应的权重值，并且A是选择的因子以提高对输入数据流的滤波的计算效率，将值{At0h0，At1h1，... 。 。 ，AtN-1hN-1}以产生相加的值{At0h0，At1h1，... 。 。 ，AtN-1hN-1}以补偿修改的滤波器抽头值并产生数字滤波器输出。 该制品包括用于执行上述方法步骤的装置。 该装置包括k级的互连系列，其中k = {1,2，...， 。 。 ，N-1}。 每个级包括具有延迟元件输入和延迟元件输出的延迟元件Zk-1，具有加权元素输入和加权元素输出的加权元件，其中加权元件的增益被选择为 实现期望的数字滤波器响应所需的增益hk，以及用于提高计算效率的因子A，以及具有第一求和单元输入，第二求和单元输入和求和单元输出的求和单元。 偏置求和元件耦合在前导增益元件和第一级求和元件之间，用于增加偏置以补偿因子加权元件增益。
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Patent Agency Ranking
6.发明授权公开(公告)号：US08694569B2
公开(公告)日：2014-04-08
申请号：US12233422
申请日：2008-09-18
Applicant: Alan N. Willson, Jr. , Tzu-Chieh Kuo
Inventor： Alan N. Willson, Jr. , Tzu-Chieh Kuo
CPC classification number: H04L27/0002 , H03M1/661 , H03M1/662
Abstract: A method and system for the design and implementation of an inverse-sinc function that can efficiently process signals produced by high-speed systems is presented. An integrated inverse-sinc module accepts multiple data streams that may result from parallel sub-systems and creates multiple outputs that can be interleaved to produce a sequence that has been filtered by an inverse-sinc function. The multiple-input, multiple-output system may be beneficially operated at a low data rate, such as the data rate used by each of the sub-systems.
Abstract translation: 提出了一种用于设计和实现可以有效处理由高速系统产生的信号的反相函数的方法和系统。 集成的反sinc模块接受可能由并行子系统产生的多个数据流，并创建可以进行交织的多个输出，以产生已被反向sinc函数过滤的序列。 多输入多输出系统可以以低数据速率有利地操作，诸如由每个子系统使用的数据速率。
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公开(公告)号：US08645443B2
公开(公告)日：2014-02-04
申请号：US12731122
申请日：2010-03-24
Applicant: Alan N. Willson, Jr.
Inventor： Alan N. Willson, Jr.
CPC classification number: H03H17/0211 , H03H17/0225 , H03H17/06 , H03H17/0657 , H03H2017/0692 , H03H2218/08
Abstract: A method and system for the design and implementation of desensitized digital filters with droop correction. The desensitized digital filter includes a first filter configured to receive an input signal, a decimator or upsampler, and a modified desensitized half-band filter. The first filter introduces droop into the passband of the desensitized digital filter. The desensitized half-band filter has a transfer function F(z)=K(1+z−1)G(z) wherein K≠0 is a scale factor, that is modified to omit a (1+z−1) factor block. The modified desensitized half-band filter compensates for the passband droop introduced by the first filter. The first filter may be a sinc filter, CIC filter, or filter having similar properties.
Abstract translation: 一种用于设计和实现具有下垂校正的脱敏数字滤波器的方法和系统。 脱敏数字滤波器包括被配置为接收输入信号的第一滤波器，抽取器或上采样器和修改的去敏化半带滤波器。 第一个滤波器将下垂引入到脱敏数字滤波器的通带中。 脱敏半带滤波器具有传递函数F（z）= K（1 + z-1）G（z）其中K <0是比例因子，其被修改为省略（1 + z-1） 因子区块 经修正的脱敏半带滤波器补偿由第一滤波器引入的通带下降。 第一过滤器可以是具有相似特性的sinc过滤器，CIC过滤器或过滤器。
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公开(公告)号：US07228325B2
公开(公告)日：2007-06-05
申请号：US09938978
申请日：2001-08-24
Applicant: Alan N. Willson, Jr. , Larry S. Wasserman
Inventor： Alan N. Willson, Jr. , Larry S. Wasserman
CPC classification number: H04L25/03834 , H03M3/462
Abstract: An adder for adding a signal at a first input (A) and a second input (B) to produce an adder output (S) is disclosed. The adder comprises a bypass input (bypass) and a logic circuit, communicatively coupled to the bypass input (bypass), the first input (A), and the second input (B), the logic circuit configured to hold at least one of the first input (A) and the second input (B) according to the bypass input (bypass).
Abstract translation: 公开了一种用于在第一输入（A）和第二输入（B）处相加信号以产生加法器输出（S）的加法器。 该加法器包括通信地耦合到旁路输入（旁路），第一输入（A）和第二输入（B）的旁路输入（旁路）和逻辑电路，逻辑电路被配置为保持至少一个 第一输入（A）和第二输入（B）根据旁路输入（旁路）。
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公开(公告)号：US09268529B2
公开(公告)日：2016-02-23
申请号：US13894321
申请日：2013-05-14
Applicant: Alan N. Willson, Jr.
Inventor： Alan N. Willson, Jr.
CPC classification number: G06F7/548 , G06F7/4818
Abstract: An apparatus and method for angle rotation is disclosed to rotate a complex input by the angle θ to produce a rotated complex output signal. A memory storage device generates control information based on a coarse angle θM. A coarse rotation butterfly circuit uses the control information to rotate the complex input signal by the coarse angle θM to produce an intermediate complex number. The control information controls one or more multiplexers and/or adders in the coarse rotation butterfly circuit to rotate the complex input signal. The fine rotation butterfly circuit uses the control information to rotate the intermediate complex number by a fine angle θL to produce the complex output signal. The control information controls one or more multiplexers and/or adders in the fine rotation butterfly circuit to rotate the intermediate complex number.
Abstract translation: 公开了一种用于角度旋转的装置和方法，以使复数输入旋转角度和角度; 以产生旋转的复数输出信号。 存储器存储装置根据粗略角度生成控制信息; M。 粗旋转蝶形电路使用控制信息使复数输入信号以粗角度＆M; M旋转以产生中间复数。 控制信息控制粗略旋转蝶形电路中的一个或多个多路复用器和/或加法器来旋转复合输入信号。 精细旋转蝶形电路使用控制信息将中间复数旋转一个微小的角度，以产生复数输出信号。 控制信息控制微旋转蝶形电路中的一个或多个多路复用器和/或加法器来旋转中间复数。
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公开(公告)号：US09244483B1
公开(公告)日：2016-01-26
申请号：US13205525
申请日：2011-08-08
Applicant: Alan N. Willson, Jr.
Inventor： Alan N. Willson, Jr.
CPC classification number: G06F1/0328 , G06F1/03 , G06F1/035
Abstract: Systems and methods for a split phase accumulator having a plurality of sub phase accumulators are provided, Each sub phase accumulator receives a portion of a frequency control word. The first sub phase accumulator includes a first register and the remaining sub phase accumulators include a register and an overflow register. At each discrete point in time, the first sub phase accumulator is configured to be responsive to the first portion of the frequency control word at that discrete point in time and to the first sub phase accumulator value at the immediately previous discrete point in time, and each of the remaining sub phase accumulators is configured to be responsive to a value of its corresponding portion of the frequency control word at that discrete point in time and to the same second sub phase accumulator value at the immediately previous discrete point in time.
Abstract translation: 提供了具有多个子相位累加器的分相相位累加器的系统和方法，每个子相位累加器接收频率控制字的一部分。 第一子相位累加器包括第一寄存器，其余子相位累加器包括寄存器和溢出寄存器。 在每个离散时间点，第一子相位累加器被配置为响应于该离散时间点处的频率控制字的第一部分以及在紧接的先前离散时间点处的第一子相位累加器值，以及 每个剩余的子相位累加器被配置为响应于在该离散时间点处的频率控制字的对应部分的值以及在紧接的先前离散时间点处的相同的第二子相位累加器值。
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