公开(公告)号：US20060288152A1

公开(公告)日：2006-12-21

申请号：US11328729

申请日：2006-01-10

Applicant: Andre Roger

Inventor： Andre Roger

IPC: G06F12/06 ,  G06F12/00

CPC classification number: G06F13/28 ,  G06F13/385

Abstract: The invention relates to a method for organizing the registers of a peripheral in memory, the peripheral including at least one control register to be addressed in memory to store configuration data of the peripheral, one transmission register to be addressed in memory to store data to be transmitted from the memory to the peripheral, and one reception register to be addressed in memory to store data to be transmitted from the peripheral to the memory, the method including: duplicating, within a data memory range, the transmission/reception register to different contiguous addresses; and implementing in memory the control registers at contiguous addresses at the level of a memory range adjacent to the memory range where the transmission/reception register has been duplicated.

Abstract translation: 本发明涉及一种用于组织存储器中外围设备的寄存器的方法，所述外围设备包括要在存储器中寻址的至少一个控制寄存器以存储外围设备的配置数据，要在存储器中寻址的一个发送寄存器以存储数据 从存储器发送到外围设备，以及一个要在存储器中寻址的接收寄存器，用于存储要从外围设备发送到存储器的数据，该方法包括：在数据存储器范围内将发送/接收寄存器复制到不同的连续 地址 并且在与发送/接收寄存器已被复制的存储器范围相邻的存储器范围内的连续地址的存储器中实现控制寄存器。

公开(公告)号：US07102383B2

公开(公告)日：2006-09-05

申请号：US10480577

申请日：2002-06-12

Applicant: Andre Roger ,  Charles Aubenas ,  Julien Fabregues

Inventor： Andre Roger ,  Charles Aubenas ,  Julien Fabregues

IPC: H03K19/177

CPC classification number: G11C16/102

Abstract: A process of programming or reprogramming a reprogrammable onboard memory (5) comprises programming or reprogramming the onboard memory of several modules (M0, M1) in parallel through a multiple access bus (6) to which the modules are connected. In the case of blank flash memories, a process downloads code through the multiple access bus (6) and executes the code, eliminating all external constraints (such as frequency, binary throughput). The process is more particularly intended to apply to onboard flash type memories.

Abstract translation: 编程或重新编程可重编程板载存储器（5）的过程包括通过与模块连接的多址总线（6）并行地编程或重新编程几个模块（M 0，M 1）的板上存储器。 在空白闪速存储器的情况下，处理通过多路访问总线（6）下载代码并执行代码，消除所有外部约束（诸如频率，二进制吞吐量）。 该过程更特别地旨在应用于板载闪存型存储器。