公开(公告)号：US07102383B2

公开(公告)日：2006-09-05

申请号：US10480577

申请日：2002-06-12

申请人： Andre Roger ,  Charles Aubenas ,  Julien Fabregues

发明人： Andre Roger ,  Charles Aubenas ,  Julien Fabregues

IPC分类号： H03K19/177

CPC分类号： G11C16/102

摘要： A process of programming or reprogramming a reprogrammable onboard memory (5) comprises programming or reprogramming the onboard memory of several modules (M0, M1) in parallel through a multiple access bus (6) to which the modules are connected. In the case of blank flash memories, a process downloads code through the multiple access bus (6) and executes the code, eliminating all external constraints (such as frequency, binary throughput). The process is more particularly intended to apply to onboard flash type memories.

摘要翻译： 编程或重新编程可重编程板载存储器（5）的过程包括通过与模块连接的多址总线（6）并行地编程或重新编程几个模块（M 0，M 1）的板上存储器。 在空白闪速存储器的情况下，处理通过多路访问总线（6）下载代码并执行代码，消除所有外部约束（诸如频率，二进制吞吐量）。 该过程更特别地旨在应用于板载闪存型存储器。

公开(公告)号：US20120030540A1

公开(公告)日：2012-02-02

申请号：US13192241

申请日：2011-07-27

申请人： Sergio Bacchin ,  Andre Roger ,  Charles Aubenas

发明人： Sergio Bacchin ,  Andre Roger ,  Charles Aubenas

IPC分类号： G06F11/08

CPC分类号： G11C11/412 ,  G06F11/1052 ,  G11C7/1006 ,  G11C11/413 ,  G11C2029/0411

摘要： An SRAM memory device including a plurality of memory cells arranged in a plurality of rows and a plurality of columns; each row of memory cells is adapted to store a RAM word; the RAM word includes a corresponding data word, a corresponding ECC word to be used for error detection and correction purposes and a corresponding applicative word to be used during debugging operations. The SRAM memory device further includes a configurable port adapted to receive a RAM word and to program corresponding memory cells of a selected row based on the received RAM word during a writing access of the SRAM memory device. The SRAM memory device further includes a memory controller unit including circuitry for selectively configuring the configurable port in one among a plurality of modes. The plurality of modes includes a first mode, wherein the configurable port is configured in such a way to disable the programming of the data word and of the corresponding ECC word of the received RAM word and at the same time enable the programming of the applicative word of the received RAM word during the writing access. The plurality of modes includes a second mode, wherein the configurable port is configured in such a way to disable the programming of the applicative word of the received RAM word and at the same time enable the programming of the data word and of the corresponding ECC word of the received RAM word during the writing access.

摘要翻译： 一种SRAM存储器件，包括以多行和多列布置的多个存储单元; 每行存储单元适于存储RAM字; RAM字包括相应的数据字，用于错误检测和校正目的的相应ECC字以及在调试操作期间使用的对应字。 SRAM存储器件还包括可配置端口，其适于在SRAM存储器件的写入访问期间基于所接收的RAM字来接收RAM字并编程所选行的相应存储器单元。 SRAM存储器装置还包括存储器控制器单元，其包括用于在多个模式之一中选择性地配置可配置端口的电路。 多个模式包括第一模式，其中可配置端口被配置为禁止数据字和所接收的RAM字的相应ECC字的编程，并且同时使得应用字的编程 在写入访问期间接收到的RAM字。 多个模式包括第二模式，其中可配置端口被配置为禁止所接收的RAM字的应用字的编程，并且同时使得能够对数据字和对应的ECC字进行编程 在写入访问期间接收到的RAM字。

公开(公告)号：US08566670B2

公开(公告)日：2013-10-22

申请号：US13192241

申请日：2011-07-27

申请人： Sergio Bacchin ,  Andre Roger ,  Charles Aubenas

发明人： Sergio Bacchin ,  Andre Roger ,  Charles Aubenas

IPC分类号： G11C29/00

CPC分类号： G11C11/412 ,  G06F11/1052 ,  G11C7/1006 ,  G11C11/413 ,  G11C2029/0411

摘要： An SRAM memory device including a plurality of memory cells arranged in a plurality of rows and a plurality of columns; each row of memory cells is adapted to store a RAM word; the RAM word includes a corresponding data word, a corresponding ECC word to be used for error detection and correction purposes and a corresponding applicative word to be used during debugging operations. The SRAM memory device further includes a configurable port adapted to receive a RAM word and to program corresponding memory cells of a selected row based on the received RAM word during a writing access of the SRAM memory device. The SRAM memory device further includes a memory controller unit including circuitry for selectively configuring the configurable port in one among a plurality of modes. The plurality of modes includes a first mode, wherein the configurable port is configured in such a way to disable the programming of the data word and of the corresponding ECC word of the received RAM word and at the same time enable the programming of the applicative word of the received RAM word during the writing access. The plurality of modes includes a second mode, wherein the configurable port is configured in such a way to disable the programming of the applicative word of the received RAM word and at the same time enable the programming of the data word and of the corresponding ECC word of the received RAM word during the writing access.

摘要翻译： 一种SRAM存储器件，包括以多行和多列布置的多个存储单元; 每行存储单元适于存储RAM字; RAM字包括相应的数据字，用于错误检测和校正目的的相应ECC字以及在调试操作期间使用的对应字。 SRAM存储器件还包括可配置端口，其适于在SRAM存储器件的写入访问期间基于所接收的RAM字来接收RAM字并编程所选行的相应存储器单元。 SRAM存储器装置还包括存储器控制器单元，其包括用于在多个模式之一中选择性地配置可配置端口的电路。 多个模式包括第一模式，其中可配置端口被配置为禁止数据字和所接收的RAM字的相应ECC字的编程，并且同时使得应用字的编程 在写入访问期间接收到的RAM字。 多个模式包括第二模式，其中可配置端口被配置为禁止所接收的RAM字的应用字的编程，并且同时使得能够对数据字和对应的ECC字进行编程 在写入访问期间接收到的RAM字。

公开(公告)号：US08805588B2

公开(公告)日：2014-08-12

申请号：US12977098

申请日：2010-12-23

申请人： Giuseppe D'Angelo ,  Fabio Marchio′ ,  Giovanni Moselli ,  Andre Roger

发明人： Giuseppe D'Angelo ,  Fabio Marchio′ ,  Giovanni Moselli ,  Andre Roger

IPC分类号： G05B13/00

CPC分类号： G06F7/5525

摘要： An embodiment is a method, and related system, to implement the square root extraction operation, which grants a 32 bits precision, which has high execution speed and is able to process a decimal radicand. An embodiment relates to a method for controlling an electric machine, comprising the detection of the value of at least one electrical quantity characterizing the machine operation and processing the detected value of said electrical quantity. The control method controls the machine operation on the basis of this processing. In particular the processing of the detected value of the electrical quantity comprises calculating a square root of a radicand value related to the detected value of electrical quantities. The calculation of the square root includes: calculating an approximated value of the square root, having a first precision, and then calculating a corrective value and combining said approximated value with said corrective value to obtain a square root value having a second precision greater than the first precision.

摘要翻译： 实施例是一种实现平方根提取操作的方法和相关系统，其提供32位精度，其具有高执行速度并能够处理小数点。 一个实施例涉及一种用于控制电机的方法，包括检测表征机器操作的至少一个电量的值并处理所述电量的检测值。 该控制方法在此处理的基础上控制机器运行。 特别地，电量检测值的处理包括计算与检测到的电量相关的根数的平方根。 平方根的计算包括：计算具有第一精度的平方根的近似值，然后计算校正值并将所述近似值与所述校正值组合以获得具有大于第二精度的第二精度的平方根值 第一精度。

公开(公告)号：US4151252A

公开(公告)日：1979-04-24

申请号：US832455

申请日：1977-09-12

申请人： Joseph Marchand ,  Andre Roger

发明人： Joseph Marchand ,  Andre Roger

IPC分类号： G01N25/48 ,  G01N25/20

CPC分类号： G01N25/4866

摘要： A heat-insulating enclosure contains temperature-regulating means and open-topped vessels each containing a sample of predetermined volume and transferred from a storage position to an analysis position in which a predetermined volume of reagent solution is contacted with the sample. Means are provided for detecting the respective temperatures of the sample and the reagent, for detecting the heat flux released and limiting thermal variations in the vicinity of each sample.

摘要翻译： 绝热外壳包含温度调节装置和敞口容器，每个容器包含预定体积的样品并从储存位置转移到预定体积的试剂溶液与样品接触的分析位置。 提供了用于检测样品和试剂的相应温度的装置，用于检测释放的热通量并限制每个样品附近的热变化。

公开(公告)号：US20130238945A1

公开(公告)日：2013-09-12

申请号：US13417382

申请日：2012-03-12

申请人： Antonio Vilela ,  Andre Roger

发明人： Antonio Vilela ,  Andre Roger

IPC分类号： G06F11/07

CPC分类号： G06F11/0763 ,  G06F11/1641 ,  G06F11/1654 ,  G06F11/1695

摘要： Embodiments relate to systems and methods for error containment in a system comprising detecting an error by processing an input signal by multiple processing units, and delaying at least one output signal of a processing unit to enable, in case an error has been detected, modifying at least one output signal of the processing unit that would cause propagation of the error through the system.

摘要翻译： 实施例涉及用于系统中的错误容纳的系统和方法，包括通过多个处理单元处理输入信号来检测错误，以及延迟处理单元的至少一个输出信号，以在检测到错误的情况下使得在 处理单元的至少一个输出信号将导致错误传播通过系统。

公开(公告)号：US4757672A

公开(公告)日：1988-07-19

申请号：US461330

申请日：1983-01-26

申请人： Andre Roger

发明人： Andre Roger

IPC分类号： A01D57/30 ,  A01D43/02

CPC分类号： A01D57/30

摘要： To form a double windrow of a grass crop after it has been cut, a windrow grouper is mounted behind a mower conditioner unit. The windrow grouper has an upright rotating drum which is provided with crop-engaging tines, and is positioned to deflect the cut crop into the double windrow when the crop is still in flight from the mower conditioner unit and before it has any substantial contact with the ground. The windrow grouper is swung clear of the crop delivered by the mower conditioner unit to enable an initial windrow to be laid, and then is swung back into the flight path of the crop to form the double windrow.

摘要翻译： 切割后，要形成草地的双重堆料，在割草机调节装置的后面安装着堆料石斑鱼。 堆料石斑鱼具有竖立的旋转鼓，其具有作物接合尖齿，并且当作物仍然从割草机调节器单元飞行并且在与割草机的任何实质接触之前，被定位成将切割的作物偏转到双层起重机 地面。 堆料石斑鱼摆脱割草机调节装置交付的作物，使初始堆放放置，然后摆回到作物的飞行路径中以形成双层料卷。

公开(公告)号：US08819485B2

公开(公告)日：2014-08-26

申请号：US13417382

申请日：2012-03-12

申请人： Antonio Vilela ,  Andre Roger

发明人： Antonio Vilela ,  Andre Roger

IPC分类号： G06F11/00

CPC分类号： G06F11/0763 ,  G06F11/1641 ,  G06F11/1654 ,  G06F11/1695

摘要： Embodiments relate to systems and methods for error containment in a system comprising detecting an error by processing an input signal by multiple processing units, and delaying at least one output signal of a processing unit to enable, in case an error has been detected, modifying at least one output signal of the processing unit that would cause propagation of the error through the system.

摘要翻译： 实施例涉及用于系统中的错误容纳的系统和方法，包括通过多个处理单元处理输入信号来检测错误，以及延迟处理单元的至少一个输出信号，以在检测到错误的情况下使得在 处理单元的至少一个输出信号将导致错误传播通过系统。

公开(公告)号：US20130207800A1

公开(公告)日：2013-08-15

申请号：US13397035

申请日：2012-02-15

申请人： Antonio Vilela ,  Andre Roger

发明人： Antonio Vilela ,  Andre Roger

IPC分类号： G08B23/00

CPC分类号： B60W50/0225 ,  B60W50/0205 ,  B60W2050/0006

摘要： An Error signal handling comprises a circuitry configured to receive an error signal from an external device indicating an error condition in the external device. The circuitry is further configured to receive a recovery signal indicating a mitigation of the error condition in the external device or indicating that a mitigation of the error condition in the external device is possible. Furthermore, the circuitry is further configured to output an error condition signal based on the error signal in response to a reception of the error signal if within a given delay time from the reception of the error signal, the circuitry does not receive the recovery signal and otherwise to omit outputting the error condition signal.

摘要翻译： 错误信号处理包括被配置为从外部设备接收指示外部设备中的错误状况的错误信号的电路。 电路还被配置为接收指示在外部设备中减轻错误状况的恢复信号，或指示可以减轻外部设备中的错误状况。 此外，电路还被配置为响应于误差信号的接收而输出基于误差信号的误差条件信号，如果在从接收到误差信号的给定延迟时间内，电路没有接收到恢复信号， 否则省略输出错误状态信号。

公开(公告)号：US20060288152A1

公开(公告)日：2006-12-21

申请号：US11328729

申请日：2006-01-10

申请人： Andre Roger

发明人： Andre Roger

IPC分类号： G06F12/06 ,  G06F12/00

CPC分类号： G06F13/28 ,  G06F13/385

摘要： The invention relates to a method for organizing the registers of a peripheral in memory, the peripheral including at least one control register to be addressed in memory to store configuration data of the peripheral, one transmission register to be addressed in memory to store data to be transmitted from the memory to the peripheral, and one reception register to be addressed in memory to store data to be transmitted from the peripheral to the memory, the method including: duplicating, within a data memory range, the transmission/reception register to different contiguous addresses; and implementing in memory the control registers at contiguous addresses at the level of a memory range adjacent to the memory range where the transmission/reception register has been duplicated.

摘要翻译： 本发明涉及一种用于组织存储器中外围设备的寄存器的方法，所述外围设备包括要在存储器中寻址的至少一个控制寄存器以存储外围设备的配置数据，要在存储器中寻址的一个发送寄存器以存储数据 从存储器发送到外围设备，以及一个要在存储器中寻址的接收寄存器，用于存储要从外围设备发送到存储器的数据，该方法包括：在数据存储器范围内将发送/接收寄存器复制到不同的连续 地址 并且在与发送/接收寄存器已被复制的存储器范围相邻的存储器范围内的连续地址的存储器中实现控制寄存器。