公开(公告)号：US06845348B1

公开(公告)日：2005-01-18

申请号：US09814417

申请日：2001-03-21

申请人： Prasad Subbarao ,  Sandeep Bhutani ,  Charutosh Dixit ,  Prabhakaran Krishnamurthy

发明人： Prasad Subbarao ,  Sandeep Bhutani ,  Charutosh Dixit ,  Prabhakaran Krishnamurthy

IPC分类号： G06F17/10 ,  G06F17/50 ,  G06F15/60

CPC分类号： G06F17/5036

摘要： A method for modeling the output waveform of a cell driving a resistance-capacitance network includes multiple effective capacitances. A method of calculating Thevenin parameters includes the steps of (a) initializing estimates of effective capacitances Ceff1 and Ceff2, of a switching threshold delay t0, and of a slope delay deltat; (b) solving ramp response equations for t0 and deltat as a function of Ceff1 and Ceff2; (c) comparing the estimates of t0 and deltat with solutions for t0 and deltat found in step (b); and (d) replacing the estimates of t0 and deltat with the solutions for t0 and deltat if the solutions for t0 and deltat have not converged to the estimates of t0 and deltat.

摘要翻译： 用于建模驱动电阻 - 电容网络的单元的输出波形的方法包括多个有效电容。 计算戴维宁参数的方法包括以下步骤：（a）初始化切换阈值延迟t0的有效电容Ceff1和Ceff2的估计值以及斜率延迟增量; （b）求解作为Ceff1和Ceff2函数的t0和deltat的斜率响应方程; （c）将t0和deltat的估计与步骤（b）中发现的t0和deltat的解决方案进行比较; 和（d）如果t0和deltat的解不会与t0和deltat的估计值相关，则用t0和deltat的解来替换t0和deltat的估计。

公开(公告)号：US20080163145A1

公开(公告)日：2008-07-03

申请号：US12046169

申请日：2008-03-11

申请人： Payman Zarkesh-Ha ,  Sandeep Bhutani ,  Weiqing Guo

发明人： Payman Zarkesh-Ha ,  Sandeep Bhutani ,  Weiqing Guo

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A method of determining whether voltage from an aggressor net exceeds a voltage threshold on a victim net design in an integrated circuit design. Probabilistic noise from the aggressor net on the victim net is calculated. The probabilistic noise is checked against the voltage threshold, and the victim net design is passed when the probabilistic noise does not exceed the voltage threshold. When the probabilistic noise does exceed the threshold, then an effective noise at a desired mean time to failure is computed, and the effective noise is checked against the voltage threshold. The victim net design is passed when the effective noise does not exceed the voltage threshold, and failed when the effective noise does exceed the threshold.

摘要翻译： 一种确定来自侵略者网络的电压是否超过集成电路设计中的受害网络设计的电压阈值的方法。 计算受害者网络上侵略者网络的概率噪声。 根据电压阈值检查概率噪声，当概率噪声不超过电压阈值时，通过受害网设计。 当概率噪声超过阈值时，计算所需的故障平均时间的有效噪声，并根据电压阈值检查有效噪声。 当有效噪声不超过电压阈值时，受害者网络设计通过，当有效噪声超过阈值时失败。

公开(公告)号：US07260801B2

公开(公告)日：2007-08-21

申请号：US11192526

申请日：2005-07-29

申请人： Sandeep Bhutani ,  Qian Cui ,  Weiqing Guo

发明人： Sandeep Bhutani ,  Qian Cui ,  Weiqing Guo

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A method of computing output delay in a mathematical model of an integrated circuit by sorting cells of original design of an the integrated circuit in a topological order. The original output delays for the sorted cells in the original design are computed in the topological order, to produce original output ramp times. The original output ramp times are propagated and original output delays are computed, and the original output ramp time and original output load for each cell is stored. The cells of the original design are modified to produce a modified design. For each modified cell in the topological order, a new output delay and a new output ramp time are computed and compared to the original output ramp time on the modified cell. When the new output ramp time substantially equals the original output ramp time for a modified cell, the calculations of the modified output ramp time for cells that are further down in the topological order are stopped. Otherwise the calculations of the modified output ramp time for cells that are further down in the topological order are continued until a cell is reached where the new output ramp time substantially equals the original output ramp time.

摘要翻译： 通过以拓扑顺序对集成电路的原始设计的单元进行排序来计算集成电路的数学模型中的输出延迟的方法。 原始设计中排序单元格的原始输出延迟以拓扑顺序计算，以产生原始输出斜坡时间。 原始输出斜坡时间被传播并且计算出原始输出延迟，并且存储每个单元的原始输出斜坡时间和原始输出负载。 原始设计的单元被修改以产生修改的设计。 对于每个修改的单元，按拓扑顺序，计算新的输出延迟和新的输出斜坡时间，并将其与修改单元上的原始输出斜坡时间进行比较。 当新的输出斜坡时间基本上等于修改的单元的原始输出斜坡时间时，停止按拓扑顺序进一步降低的单元的修改的输出斜坡时间的计算。 否则，继续按照拓扑顺序进一步降低的单元的修改的输出斜坡时间的计算，直到达到单元，其中新的输出斜坡时间基本上等于原始输出斜坡时间。

公开(公告)号：US20060190859A1

公开(公告)日：2006-08-24

申请号：US11061581

申请日：2005-02-18

申请人： Qian Cui ,  Sandeep Bhutani

发明人： Qian Cui ,  Sandeep Bhutani

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/5036

摘要： A method for accounting for negative bias temperature instability in a rise delay of a circuit design, the method comprising the steps of create a cell and net model library with original rise numbers, construct the circuit design from the cell and net models, for each cell and net in the circuit design, calculate an original rise delay, apply a negative bias temperature instability model to determine a parameter shift, determine a new rise number from the parameter shift, and calculate a new rise delay by original rise delay*(original rise number)/(new rise number).

摘要翻译： 一种用于计算电路设计的上升延迟中的负偏压温度不稳定性的方法，所述方法包括以下步骤：创建具有原始上升数的单元和网模型库，为每个单元构建单元和网模型的电路设计 并在电路设计中，计算原始上升延迟，应用负偏置温度不稳定模型确定参数偏移，从参数偏移确定新的上升数，并通过原始上升延迟计算新的上升延迟*（原始上升 数字）/（新上升数）。

公开(公告)号：US07069178B2

公开(公告)日：2006-06-27

申请号：US10955168

申请日：2004-09-29

申请人： Qian Cui ,  Sandeep Bhutani

发明人： Qian Cui ,  Sandeep Bhutani

IPC分类号： G06F3/01

CPC分类号： G01R31/3008

摘要： In exemplary embodiments, a method and computer program product for predicting quiescent current variation of an integrated circuit die include steps of: (a) receiving as input a value of a derating factor from a process monitor cell on an integrated circuit die and an on-chip variation of the derating factor; (b) constructing a curve fitting formula for estimating a quiescent current of the integrated circuit die as a function of the derating factor; (c) calculating minimum and maximum values of the quiescent current from the curve fitting formula, the value of the derating factor from the process monitor cell, and the on-chip variation of the derating factor to generate an estimate of minimum and maximum values for the quiescent current; and (d) generating as output the estimated minimum and maximum values of the quiescent current.

公开(公告)号：US06587999B1

公开(公告)日：2003-07-01

申请号：US09859149

申请日：2001-05-15

申请人： Lei Chen ,  Sandeep Bhutani ,  Nianging Zhang

发明人： Lei Chen ,  Sandeep Bhutani ,  Nianging Zhang

IPC分类号： G06F945

CPC分类号： G06F17/5022

摘要： A method of modeling delays in an integrated circuit design is disclosed that may be used to reduce the computation time of path delays in an integrated circuit design. A method of modeling delays in an integrated circuit design includes the steps of receiving as input a description of an integrated circuit design; identifying at least one small net in the integrated circuit design from the description; approximating an effective capacitance of the at least one small net by the total capacitance; and approximating an interconnect delay of the at least one small net by zero.

摘要翻译： 公开了一种用于集成电路设计中的延迟建模的方法，其可用于减少集成电路设计中的路径延迟的计算时间。 一种对集成电路设计中的延迟进行建模的方法包括以下步骤：接收作为输入的集成电路设计的描述; 从描述中识别集成电路设计中的至少一个小网; 将所述至少一个小网的有效电容近似于总电容; 以及将所述至少一个小网络的互连延迟近似为零。

公开(公告)号：US07577928B2

公开(公告)日：2009-08-18

申请号：US11376781

申请日：2006-03-15

申请人： Peter Lindberg ,  Richard K. Kirchner ,  Sandeep Bhutani

发明人： Peter Lindberg ,  Richard K. Kirchner ,  Sandeep Bhutani

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A system, apparatus and method for generating and validating extracted timing model files, such as macro library files, are disclosed. A user interface or data template is provided to an engineer that allows for the population of data within particular fields related to timing characteristics of an IP block, cell or core. An extracted timing model file is generated and a validation procedure is performed. This validation procedure may include comparing the information with the file to a test bench have a plurality of test points. In particular, data provided by the engineer is checked against multiple criteria to ensure that this data is valid and/or falls within an appropriate value range constraints. After the validation procedure has completed, the engineer is provided a summary of the validation results.

摘要翻译： 公开了一种用于生成和验证提取的定时模型文件（诸如宏库文件）的系统，装置和方法。 将用户界面或数据模板提供给允许在与IP块，单元或核心的定时特性相关的特定领域内的数据的总体的工程师。 生成提取的定时模型文件，并执行验证过程。 该验证过程可以包括将信息与文件进行比较，以具有多个测试点。 特别地，由多个标准检查由工程师提供的数据，以确保该数据有效和/或落入适当的值范围约束。 验证程序完成后，工程师将提供验证结果的摘要。

公开(公告)号：US07376918B2

公开(公告)日：2008-05-20

申请号：US11079017

申请日：2005-03-11

申请人： Payman Zarkesh-Ha ,  Sandeep Bhutani ,  Weiqing Guo

发明人： Payman Zarkesh-Ha ,  Sandeep Bhutani ,  Weiqing Guo

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A method of determining whether voltage from an aggressor net exceeds a voltage threshold on a victim net design in an integrated circuit design. Probabilistic noise from the aggressor net on the victim net is calculated. The probabilistic noise is checked against the voltage threshold, and the victim net design is passed when the probabilistic noise does not exceed the voltage threshold. When the probabilistic noise does exceed the threshold, then an effective noise at a desired mean time to failure is computed, and the effective noise is checked against the voltage threshold. The victim net design is passed when the effective noise does not exceed the voltage threshold, and failed when the effective noise does exceed the threshold.

摘要翻译： 一种确定来自侵略者网络的电压是否超过集成电路设计中的受害网络设计的电压阈值的方法。 计算受害者网络上侵略者网络的概率噪声。 根据电压阈值检查概率噪声，当概率噪声不超过电压阈值时，通过受害网设计。 当概率噪声超过阈值时，计算所需的故障平均时间的有效噪声，并根据电压阈值检查有效噪声。 当有效噪声不超过电压阈值时，受害者网络设计通过，当有效噪声超过阈值时失败。

公开(公告)号：US20070186198A1

公开(公告)日：2007-08-09

申请号：US11351091

申请日：2006-02-09

申请人： Peter Lindberg ,  Richard Kirchner ,  Sandeep Bhutani

发明人： Peter Lindberg ,  Richard Kirchner ,  Sandeep Bhutani

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A system, apparatus and method for generating extracted timing model files, such as macro library files, are disclosed. A user interface or data template is provided to an engineer that allows for the population of data within particular fields related to timing characteristics of an IP block, cell or core. Various types of data and fields may be provided into the user interface or data template. The location of relevant files, such as a cell or core netlist, may be provided within the template. Additionally, one or more modes may be selected by the user to define the manner in which the ETM file(s) are to be generated. An ETM file is automatically generated using the information provided in the data template.

摘要翻译： 公开了一种用于产生提取的定时模型文件（诸如宏库文件）的系统，装置和方法。 将用户界面或数据模板提供给允许在与IP块，单元或核心的定时特性相关的特定领域内的数据的总体的工程师。 可以将各种类型的数据和字段提供给用户界面或数据模板。 可以在模板内提供相关文件的位置，例如单元格或核心网表。 此外，用户可以选择一个或多个模式来定义要生成ETM文件的方式。 使用数据模板中提供的信息自动生成ETM文件。

公开(公告)号：US07228516B2

公开(公告)日：2007-06-05

申请号：US11061581

申请日：2005-02-18

申请人： Qian Cui ,  Sandeep Bhutani

发明人： Qian Cui ,  Sandeep Bhutani

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/5036

摘要： A method for accounting for negative bias temperature instability in a rise delay of a circuit design, the method comprising the steps of create a cell and net model library with original rise numbers, construct the circuit design from the cell and net models, for each cell and net in the circuit design, calculate an original rise delay, apply a negative bias temperature instability model to determine a parameter shift, determine a new rise number from the parameter shift, and calculate a new rise delay by original rise delay* (original rise number)/(new rise number).

摘要翻译： 一种用于计算电路设计的上升延迟中的负偏压温度不稳定性的方法，所述方法包括以下步骤：创建具有原始上升数的单元和网模型库，为每个单元构建单元和网模型的电路设计 并在电路设计中，计算原始上升延迟，应用负偏置温度不稳定模型确定参数偏移，从参数偏移确定新的上升数，并通过原始上升延迟计算新的上升延迟*（原始上升 数字）/（新上升数）。