公开(公告)号：US20140201698A1

公开(公告)日：2014-07-17

申请号：US14217570

申请日：2014-03-18

Applicant: Apple Inc.

Inventor： Shingo Suzuki ,  Karthik Rajagopal ,  Bo Tang

IPC: G06F17/50

CPC classification number: G06F17/5072

Abstract: A method of generating an area efficient power switch cell includes receiving, by a cell library design tool, a specification of a power switch circuit to be established as a power switch cell in a cell library. The cell library design tool also receives one or more attributes of the power switch cell including a height of the cell boundary and receiving, by the cell library design tool, a layout placement constraint requiring the power switch cell to be placed in a semiconductor layout so as to bridge two parallel rows of doped wells. The parallel rows of doped wells are interleaved with doped substrate and the doping of the wells is of a different type than that of the substrate. Based on the specification of the power switch circuit, the one or more attributes, and the layout placement constraint, the cell library design tool generates the power switch cell.