公开(公告)号：US08726216B2

公开(公告)日：2014-05-13

申请号：US13628581

申请日：2012-09-27

Applicant: Apple Inc.

Inventor： Shingo Suzuki ,  Karthik Rajagopal ,  Bo Tang

IPC: G06F17/50

CPC classification number: G06F17/5072

Abstract: A method of generating an area efficient power switch cell includes receiving, by a cell library design tool, a specification of a power switch circuit to be established as a power switch cell in a cell library. The cell library design tool also receives one or more attributes of the power switch cell including a height of the cell boundary and receiving, by the cell library design tool, a layout placement constraint requiring the power switch cell to be placed in a semiconductor layout so as to bridge two parallel rows of doped wells. The parallel rows of doped wells are interleaved with doped substrate and the doping of the wells is of a different type than that of the substrate. Based on the specification of the power switch circuit, the one or more attributes, and the layout placement constraint, the cell library design tool generates the power switch cell.

Abstract translation: 一种产生区域有效的功率开关单元的方法包括：由单元库设计工具接收要建立为单元库中的功率开关单元的功率开关电路的规格。 单元库设计工具还接收包括单元边界的高度的功率开关单元的一个或多个属性，并且由单元库设计工具接收布局布局约束，其要求将功率开关单元放置在半导体布局中，从而 桥接两排平行的掺杂阱。 掺杂阱的平行行与掺杂衬底交错，并且阱的掺杂与衬底的掺杂不同。 基于功率开关电路的规格，一个或多个属性和布局布局约束，单元库设计工具生成电源开关单元。

公开(公告)号：US20140089883A1

公开(公告)日：2014-03-27

申请号：US13628581

申请日：2012-09-27

Applicant: APPLE INC.

Inventor： Shingo Suzuki ,  Karthik Rajagopal ,  Bo Tang

IPC: G06F17/50

CPC classification number: G06F17/5072

Abstract: A method of generating an area efficient power switch cell includes receiving, by a cell library design tool, a specification of a power switch circuit to be established as a power switch cell in a cell library. The cell library design tool also receives one or more attributes of the power switch cell including a height of the cell boundary and receiving, by the cell library design tool, a layout placement constraint requiring the power switch cell to be placed in a semiconductor layout so as to bridge two parallel rows of doped wells. The parallel rows of doped wells are interleaved with doped substrate and the doping of the wells is of a different type than that of the substrate. Based on the specification of the power switch circuit, the one or more attributes, and the layout placement constraint, the cell library design tool generates the power switch cell.

Abstract translation: 一种产生区域有效的功率开关单元的方法包括：由单元库设计工具接收要建立为单元库中的功率开关单元的功率开关电路的规格。 单元库设计工具还接收包括单元边界的高度的功率开关单元的一个或多个属性，并且由单元库设计工具接收布局布局约束，其要求将功率开关单元放置在半导体布局中，从而 桥接两排平行的掺杂阱。 掺杂阱的平行行与掺杂衬底交错，并且阱的掺杂与衬底的掺杂不同。 基于功率开关电路的规格，一个或多个属性和布局布局约束，单元库设计工具生成电源开关单元。

公开(公告)号：US20160085900A1

公开(公告)日：2016-03-24

申请号：US14492923

申请日：2014-09-22

Applicant: Apple Inc.

Inventor： Amit Chandra ,  Karthik Rajagopal ,  Muthukumaravelu Velayoudame ,  Praveen Bhutani ,  Sunil Mehta

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5036 ,  G06F17/5081 ,  G06F2217/78

Abstract: In an embodiment, a methodology for designing an integrated circuit that attempts to improve power efficiency is provided. The methodology includes simulating the design under one or more power stimuli, where the power stimuli are known to cause high power consumption (e.g. in previous designs of the integrated circuit, the power stimuli may have caused power consumption). A set of nets within the integrated circuit may be identified that have the highest activity in the simulation (e.g. the highest amount of switching). The methodology may include providing data to the routing tool that is to route the nets in the integrated circuit. The data may indicate constraints for the set of nets, to help reduce dynamic power on these nets. Power efficiency of the integrated circuit may be improved if the routing tool is able to honor the constraints.

Abstract translation: 在一个实施例中，提供了一种用于设计试图提高功率效率的集成电路的方法。 该方法包括模拟在一个或多个功率刺激下的设计，其中功率刺激已知导致高功率消耗（例如在集成电路的先前设计中，功率刺激可能已经引起功率消耗）。 在集成电路中可以识别出在仿真中具有最高活动性（例如最高切换量）的网络集合。 该方法可以包括向布线工具提供数据以将集线器中的网络路由。 数据可能表示网络集合的约束，以帮助减少这些网络的动态功率。 如果路由工具能够遵守约束，则可以提高集成电路的功率效率。

公开(公告)号：US09189586B2

公开(公告)日：2015-11-17

申请号：US14217570

申请日：2014-03-18

Applicant: Apple Inc.

Inventor： Shingo Suzuki ,  Karthik Rajagopal ,  Bo Tang

IPC: G06F17/50

CPC classification number: G06F17/5072

Abstract: A method of generating an area efficient power switch cell includes receiving, by a cell library design tool, a specification of a power switch circuit to be established as a power switch cell in a cell library. The cell library design tool also receives one or more attributes of the power switch cell including a height of the cell boundary and receiving, by the cell library design tool, a layout placement constraint requiring the power switch cell to be placed in a semiconductor layout so as to bridge two parallel rows of doped wells. The parallel rows of doped wells are interleaved with doped substrate and the doping of the wells is of a different type than that of the substrate. Based on the specification of the power switch circuit, the one or more attributes, and the layout placement constraint, the cell library design tool generates the power switch cell.

Abstract translation: 一种产生区域有效的功率开关单元的方法包括：由单元库设计工具接收要建立为单元库中的功率开关单元的功率开关电路的规格。 单元库设计工具还接收包括单元边界的高度的功率开关单元的一个或多个属性，并且由单元库设计工具接收布局布局约束，其要求将功率开关单元放置在半导体布局中，从而 桥接两排平行的掺杂阱。 掺杂阱的平行行与掺杂衬底交错，并且阱的掺杂与衬底的掺杂不同。 基于功率开关电路的规格，一个或多个属性和布局布局约束，单元库设计工具生成电源开关单元。

公开(公告)号：US09607125B1

公开(公告)日：2017-03-28

申请号：US14732971

申请日：2015-06-08

Applicant: Apple Inc.

Inventor： Antonietta Oliva ,  Karthik Rajagopal ,  Manoj Gopalan ,  Mini Nanua ,  Sambasivan Narayan

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F2217/76

Abstract: Embodiments of an electromigration (EM) check scheme to reduce a pessimism on current density limits by checking wire context. This methodology, in an embodiment, includes applying existing electronic design automation (EDA) flows and tools to identify potentially-failing wires based on a worst-case EM check using conservative foundry current density limits. A more accurate, context-specific check can be performed on the potentially-failing wires to eliminate one or more of the potentially-failing wires if those wires do not experience worst-case conditions and meet current density limits based on an actual context of those wires. A designer can correct remaining wires which are not eliminated by the context-specific check.

公开(公告)号：US09292648B1

公开(公告)日：2016-03-22

申请号：US14492923

申请日：2014-09-22

Applicant: Apple Inc.

Inventor： Amit Chandra ,  Karthik Rajagopal ,  Muthukumaravelu Velayoudame ,  Praveen Bhutani ,  Sunil Mehta

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5036 ,  G06F17/5081 ,  G06F2217/78

Abstract: In an embodiment, a methodology for designing an integrated circuit that attempts to improve power efficiency is provided. The methodology includes simulating the design under one or more power stimuli, where the power stimuli are known to cause high power consumption (e.g. in previous designs of the integrated circuit, the power stimuli may have caused power consumption). A set of nets within the integrated circuit may be identified that have the highest activity in the simulation (e.g. the highest amount of switching). The methodology may include providing data to the routing tool that is to route the nets in the integrated circuit. The data may indicate constraints for the set of nets, to help reduce dynamic power on these nets. Power efficiency of the integrated circuit may be improved if the routing tool is able to honor the constraints.

Abstract translation: 在一个实施例中，提供了一种用于设计试图提高功率效率的集成电路的方法。 该方法包括模拟在一个或多个功率刺激下的设计，其中功率刺激已知导致高功率消耗（例如在集成电路的先前设计中，功率刺激可能已经引起功率消耗）。 在集成电路中可以识别出在仿真中具有最高活动性（例如最高切换量）的网络集合。 该方法可以包括向布线工具提供数据以将集线器中的网络路由。 数据可能表示网络集合的约束，以帮助减少这些网络的动态功率。 如果路由工具能够遵守约束，则可以提高集成电路的功率效率。

公开(公告)号：US09817937B2

公开(公告)日：2017-11-14

申请号：US14880420

申请日：2015-10-12

Applicant: Apple Inc.

Inventor： Shingo Suzuki ,  Karthik Rajagopal ,  Bo Tang

IPC: G06F17/50

CPC classification number: G06F17/5072

Abstract: A method of generating an area efficient power switch cell includes receiving, by a cell library design tool, a specification of a power switch circuit to be established as a power switch cell in a cell library. The cell library design tool also receives one or more attributes of the power switch cell including a height of the cell boundary and receiving, by the cell library design tool, a layout placement constraint requiring the power switch cell to be placed in a semiconductor layout so as to bridge two parallel rows of doped wells. The parallel rows of doped wells are interleaved with doped substrate and the doping of the wells is of a different type than that of the substrate. Based on the specification of the power switch circuit, the one or more attributes, and the layout placement constraint, the cell library design tool generates the power switch cell.

公开(公告)号：US09823688B2

公开(公告)日：2017-11-21

申请号：US14681599

申请日：2015-04-08

Applicant: Apple Inc.

Inventor： Karthik Rajagopal ,  Narayanan V. Thondugulam ,  Rahul Sharma

IPC: G06F17/50 ,  G06F1/10

CPC classification number: G06F1/10 ,  G06F17/505 ,  G06F2217/62

Abstract: A method for designing a clock tree is disclosed. In one embodiment, a preliminary clock tree design for an integrated circuit (IC) is processed. The clock tree includes a root node, a number of intermediate levels, and a leaf level that is coupled to a number of clocked circuits. Clock gating circuits are placed at the leaf level of the clock tree, and at least some of the intermediate levels. Processing the preliminary clock tree design includes ensuring that an equal number of clock gating circuits are coupled between each leaf level clock gating circuit and the root node. After processing the preliminary clock tree design, clock tree synthesis is performed by executing a clock tree synthesis tool on a computer system to generate a synthesized clock tree design.

公开(公告)号：US20160299524A1

公开(公告)日：2016-10-13

申请号：US14681599

申请日：2015-04-08

Applicant: Apple Inc.

Inventor： Karthik Rajagopal ,  Narayanan V. Thondugulam ,  Rahul Sharma

IPC: G06F1/10 ,  G06F17/50

CPC classification number: G06F1/10 ,  G06F17/505 ,  G06F2217/62

Abstract: A method for designing a clock tree is disclosed. In one embodiment, a preliminary clock tree design for an integrated circuit (IC) is processed. The clock tree includes a root node, a number of intermediate levels, and a leaf level that is coupled to a number of clocked circuits. Clock gating circuits are placed at the leaf level of the clock tree, and at least some of the intermediate levels. Processing the preliminary clock tree design includes ensuring that an equal number of clock gating circuits are coupled between each leaf level clock gating circuit and the root node. After processing the preliminary clock tree design, clock tree synthesis is performed by executing a clock tree synthesis tool on a computer system to generate a synthesized clock tree design.

Abstract translation: 公开了一种用于设计时钟树的方法。 在一个实施例中，处理集成电路（IC）的初步时钟树设计。 时钟树包括根节点，多个中间电平以及耦合到多个时钟电路的叶电平。 时钟门控电路放置在时钟树的叶级，至少部分中间级。 处理初步时钟树设计包括确保在每个叶级时钟选通电路和根节点之间耦合相等数量的时钟门控电路。 在处理初步时钟树设计之后，通过在计算机系统上执行时钟树合成工具来执行时钟树合成，以产生合成时钟树设计。

公开(公告)号：US20160034630A1

公开(公告)日：2016-02-04

申请号：US14880420

申请日：2015-10-12

Applicant: Apple Inc.

Inventor： Shingo Suzuki ,  Karthik Rajagopal ,  Bo Tang

IPC: G06F17/50

CPC classification number: G06F17/5072

Abstract: A method of generating an area efficient power switch cell includes receiving, by a cell library design tool, a specification of a power switch circuit to be established as a power switch cell in a cell library. The cell library design tool also receives one or more attributes of the power switch cell including a height of the cell boundary and receiving, by the cell library design tool, a layout placement constraint requiring the power switch cell to be placed in a semiconductor layout so as to bridge two parallel rows of doped wells. The parallel rows of doped wells are interleaved with doped substrate and the doping of the wells is of a different type than that of the substrate. Based on the specification of the power switch circuit, the one or more attributes, and the layout placement constraint, the cell library design tool generates the power switch cell.

Abstract translation: 一种产生区域有效的功率开关单元的方法包括：由单元库设计工具接收要建立为单元库中的功率开关单元的功率开关电路的规格。 单元库设计工具还接收包括单元边界的高度的功率开关单元的一个或多个属性，并且由单元库设计工具接收布局布局约束，其要求将功率开关单元放置在半导体布局中，从而 桥接两排平行的掺杂阱。 掺杂阱的平行行与掺杂衬底交错，并且阱的掺杂与衬底的掺杂不同。 基于功率开关电路的规格，一个或多个属性和布局布局约束，单元库设计工具生成电源开关单元。