公开(公告)号：US20080127018A1

公开(公告)日：2008-05-29

申请号：US11554637

申请日：2006-10-31

申请人： Charles J. Alpert ,  David J. Hathaway ,  William R. Migatz ,  Gi-Joon Nam ,  Haoxing Ren ,  Paul G. Villarrubia

发明人： Charles J. Alpert ,  David J. Hathaway ,  William R. Migatz ,  Gi-Joon Nam ,  Haoxing Ren ,  Paul G. Villarrubia

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： The layout of latches in a common clock domain is efficiently optimized to shrink the physical size of the domain while maintaining timing requirements. The latches are placed in a first layout preferably using quadratic placement, and a star object is built representing an interim clock structure. The latches are weighted based on wire distance from a source of the star object, and then re-placed using the weighting. The weighted placement and repartitioning may be iteratively repeated until a target number of bins is reached. The boundary of the latches in the final global placement is used to define a movebound for further detailed placement.

摘要翻译： 锁存器在公共时钟域中的布局被有效优化，以缩小域的物理大小，同时保持时序要求。 锁存器优选地使用二次放置放置在第一布局中，并且构建代表中间时钟结构的星形物体。 锁存器根据与星形物体源的线距离进行加权，然后使用加权重新放置。 可以迭代地重复加权放置和重新分配，直到达到目标数量的箱。 最终全局放置中的锁存器的边界用于定义移动以进一步详细放置。

公开(公告)号：US08495534B2

公开(公告)日：2013-07-23

申请号：US12796550

申请日：2010-06-08

申请人： Charles J. Alpert ,  Zhuo D. Li ,  Gi-Joon Nam ,  Shyam Ramji ,  Lakshmi N. Reddy ,  Jarrod A. Roy ,  Taraneh E. Taghavi ,  Paul G. Villarrubia ,  Natarajan Viswanathan

发明人： Charles J. Alpert ,  Zhuo D. Li ,  Gi-Joon Nam ,  Shyam Ramji ,  Lakshmi N. Reddy ,  Jarrod A. Roy ,  Taraneh E. Taghavi ,  Paul G. Villarrubia ,  Natarajan Viswanathan

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that has high detailed routing costs. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell in a selected tile. The expander applies multiple techniques to reposition these cells at new locations to improve the detailed routability. The expander can place an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile, and repositions the selected cell within the bounding box to form a modified design to improve the detailed routability. The expander may also inflate and legalize those cells.

摘要翻译： 一种计算机实现的方法，数据处理系统和用于重新设计最初放置在电路设计中的多个单元的计算机程序产品。 扩展器将单元格分配给图块。 扩展器确定高度详细的路由成本瓦片类，其中高详细路由成本瓦片类是具有高详细路由成本的一类瓦片。 扩展器选择高详细路由代价块类别的块内的单元，以在所选择的块中形成选定的单元。 扩展器应用多种技术在新位置重新定位这些单元，以提高详细的可布线性。 扩展器可以在所选择的单元周围放置扩展的边界框，其中边界框延伸到与所选择的瓦片相邻的至少一个瓦片，并且在边界框内重新定位所选择的单元以形成修改的设计以改进详细的可布线性。 扩张器也可能使这些细胞膨胀并合法化。

公开(公告)号：US08347257B2

公开(公告)日：2013-01-01

申请号：US12796501

申请日：2010-06-08

申请人： Charles J. Alpert ,  Andrew D. Huber ,  Zhuo Li ,  Gi-Joon Nam ,  Shyam Ramji ,  Jarrod A. Roy ,  Taraneh E. Taghavi ,  Gustavo E. Tellez ,  Paul G. Villarrubia ,  Natarajan Viswanathan

发明人： Charles J. Alpert ,  Andrew D. Huber ,  Zhuo Li ,  Gi-Joon Nam ,  Shyam Ramji ,  Jarrod A. Roy ,  Taraneh E. Taghavi ,  Gustavo E. Tellez ,  Paul G. Villarrubia ,  Natarajan Viswanathan

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles, wherein some tiles have cells. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that are high detailed routing cost tiles. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell and a selected tile. The expander places an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile. The expander expands the selected cell within the bounding box to form a modified design, determines an aggregate routing cost among other steps, and affirms the modified design for further processing.

摘要翻译： 一种计算机实现的方法，数据处理系统和用于重新设计最初放置在电路设计中的多个单元的计算机程序产品。 扩展器将单元格分配给图块，其中某些图块具有单元格。 扩展器确定高详细路由成本瓦片类，其中高详细路由成本瓦片类是作为高详细路由成本瓦片的瓦片类。 扩展器选择高详细路由代价块类别的块内的单元，以形成所选择的单元和所选择的块。 扩展器将扩展的边界框放置在所选择的单元周围，其中边界框延伸到与所选择的瓦片相邻的至少一个瓦片。 扩展器在边界框内扩展所选单元格以形成修改的设计，确定其他步骤之间的汇总路由成本，并确认修改后的设计以进行进一步处理。

公开(公告)号：US20110302544A1

公开(公告)日：2011-12-08

申请号：US12796550

申请日：2010-06-08

申请人： Charles J. Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  Shyam Ramji ,  Lakshmi N. Reddy ,  Jarrod A. Roy ,  Taraneh Taghavi ,  Paul G. Villarrubia ,  Natarajan Viswanathan

发明人： Charles J. Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  Shyam Ramji ,  Lakshmi N. Reddy ,  Jarrod A. Roy ,  Taraneh Taghavi ,  Paul G. Villarrubia ,  Natarajan Viswanathan

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that has high detailed routing costs. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell in a selected tile. The expander applies multiple techniques to reposition these cells at new locations to improve the detailed routability. The expander can place an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile, and repositions the selected cell within the bounding box to form a modified design to improve the detailed routability. The expander may also inflate and legalize those cells.

摘要翻译： 一种计算机实现的方法，数据处理系统和用于重新设计最初放置在电路设计中的多个单元的计算机程序产品。 扩展器将单元格分配给图块。 扩展器确定高度详细的路由成本瓦片类，其中高详细路由成本瓦片类是具有高详细路由成本的一类瓦片。 扩展器选择高详细路由代价块类别的块内的单元，以在所选择的块中形成选定的单元。 扩展器应用多种技术在新位置重新定位这些单元，以提高详细的可布线性。 扩展器可以在所选择的单元周围放置扩展的边界框，其中边界框延伸到与所选择的瓦片相邻的至少一个瓦片，并且在边界框内重新定位所选择的单元以形成修改的设计以改进详细的可布线性。 扩张器也可能使这些细胞膨胀并合法化。

公开(公告)号：US07549137B2

公开(公告)日：2009-06-16

申请号：US11610567

申请日：2006-12-14

申请人： Charles J. Alpert ,  Shyam Ramji ,  Chin Ngai Sze ,  Paul G. Villarrubia

发明人： Charles J. Alpert ,  Shyam Ramji ,  Chin Ngai Sze ,  Paul G. Villarrubia

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A novel iterative latch placement scheme wherein the latches are gradually pulled by increasing attraction force until they are eventually placed next to a clock distribution structure such as a local clock buffer (LCB). During the iterations, timing optimizations such as gate sizing and re-buffering are invoked in order to keep the timing estimation accurate. By applying the iterative clock net weighting adjustment, the present invention allows tighter interaction between logic placement and clock placement which leads to higher quality timing and significant power savings.

摘要翻译： 一种新颖的迭代锁存器放置方案，其中锁存器通过增加吸引力而逐渐拉动，直到它们最终被放置在诸如本地时钟缓冲器（LCB）之类的时钟分布结构旁边。 在迭代期间，调用诸如门尺寸和重新缓冲之类的定时优化，以便使时序估计保持准确。 通过应用迭代时钟网络加权调整，本发明允许逻辑放置和时钟布置之间的更紧密的交互，这导致更高的质量定时和显着的功率节省。

公开(公告)号：US20080066037A1

公开(公告)日：2008-03-13

申请号：US11531322

申请日：2006-09-13

申请人： Charles J. Alpert ,  Gi-Joon Nam ,  Haoxing Ren ,  Paul G. Villarrubia ,  Natarajan Viswanathan

发明人： Charles J. Alpert ,  Gi-Joon Nam ,  Haoxing Ren ,  Paul G. Villarrubia ,  Natarajan Viswanathan

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A method of force directed placement programming is presented. The method includes sorting objects of a netlist for placement by magnitude of their spreading force and selecting a plurality of the objects. The method further includes waiving (or nullifying) the spreading force for the selected objects in a subsequent non-linear program solver step of the force directed placement program. The positions of the objects after the subsequent non-linear program solver step are based only on their connections to other objects in the netlist. The selected objects no longer retain their relative ordering as obtained during a previous non-linear program solve step of the force directed placement program. An alternative method of force directed placement programming is also present, which includes identifying objects from a netlist for placement that have a very high spreading force magnitude. The method further includes controlling the spreading force magnitude for the objects identified in the force directed placement programming to reduce wirelength in a chip design without sacrificing spreading of the objects.

摘要翻译： 提出了一种强制定向布置程序的方法。 该方法包括对网表的对象进行排序，以便按照其展开力的大小进行放置并选择多个对象。 该方法还包括在力定向放置程序的随后非线性程序解算器步骤中放弃（或消除）所选对象的展开力。 在后续非线性程序求解器步骤之后的对象的位置仅基于它们与网表中其他对象的连接。 所选择的对象不再保留在力定向放置程序的先前非线性程序解决步骤中获得的相对排序。 还存在一种替代的力定向放置编程的方法，其包括从具有非常高的铺展力量级的用于放置的网表识别对象。 该方法还包括控制在力定向放置编程中识别的物体的展开力大小以减少芯片设计中的线长度，而不牺牲物体的扩展。

公开(公告)号：US20120284733A1

公开(公告)日：2012-11-08

申请号：US13550957

申请日：2012-07-17

申请人： Gi-Joon Nam ,  Shyam Ramji ,  Taraneh Taghavi ,  Paul G. Villarrubia

发明人： Gi-Joon Nam ,  Shyam Ramji ,  Taraneh Taghavi ,  Paul G. Villarrubia

IPC分类号： G06F9/46

CPC分类号： G06F17/50 ,  G06F9/5066

摘要： Scheduling of parallel processing for regionally-constrained object placement selects between different balancing schemes. For a small number of movebounds, computations are assigned by balancing the placeable objects. For a small number of objects per movebound, computations are assigned by balancing the movebounds. If there are large numbers of movebounds and objects per movebound, both objects and movebounds are balanced amongst the processors. For object balancing, movebounds are assigned to a processor until an amortized number of objects for the processor exceeds a first limit above an ideal number, or the next movebound would raise the amortized number of objects above a second, greater limit. For object and movebound balancing, movebounds are sorted into descending order, then assigned in the descending order to host processors in successive rounds while reversing the processor order after each round. The invention provides a schedule in polynomial-time while retaining high quality of results.

摘要翻译： 区域约束对象放置的并行处理调度在不同的平衡方案之间进行选择。 对于少量的移动端口，通过平衡可放置对象来分配计算。 对于每次移动的少量对象，通过平衡移动端口分配计算。 如果每次移动都有大量的移动和对象，则处理器之间的对象和移动对象都是平衡的。 对于对象平衡，移动端口被分配给一个处理器，直到处理器的摊销对象数量超过理想数量以上的第一个限制，或者下一个移动端口将提高超过第二个更大限制的对象数量。 对于对象和移动平衡，移动排列按降序排列，然后按顺序分配给主机处理器，连续回合，同时在每轮之后反转处理器顺序。 本发明提供多项式时间的时间表，同时保持高质量的结果。

公开(公告)号：US20080209376A1

公开(公告)日：2008-08-28

申请号：US11680110

申请日：2007-02-28

申请人： Michael A. Kazda ,  Pooja M. Kotecha ,  Adam P. Matheny ,  Lakshmi Reddy ,  Louise H. Trevillyan ,  Paul G. Villarrubia

发明人： Michael A. Kazda ,  Pooja M. Kotecha ,  Adam P. Matheny ,  Lakshmi Reddy ,  Louise H. Trevillyan ,  Paul G. Villarrubia

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/84

摘要： A method for performing timing optimization of a detail routed netlist, incorporating statistical variability information, common path pessimism reduction, and capacitative coupling information, in a tightly coupled, incremental manner with minimal perturbations to the placement, routing, and asserted parasitic information. The method corrects violations in a placed and routed design of a VLSI circuit chip, where the design is represented by a netlist describing logical and physical characteristics of the design and by a corresponding timing graph, the method including the steps of: identifying violations in the design; iteratively eliminating the violations by incrementally transforming the logical and the physical characteristics of the design, incorporating in the design only legal placements and routes; and applying incremental timing to evaluate the transformations, and updating the existing timing graphs to reflect changes consisting of the legal placements and routes.

摘要翻译： 一种用于以紧密耦合的递增方式对细节路由网表执行定时优化的方法，其以最小的扰动对放置，路由和断言的寄生信息进行并入，并入统计变异信息，公共路径悲观度降低和电容耦合信息。 该方法校正了VLSI电路芯片的放置和路由设计中的违规，其中设计由描述设计的逻辑和物理特性的网表以及对应的时序图表示，该方法包括以下步骤：识别 设计; 通过逐步改变设计的逻辑和物理特征，迭代地消除违规行为，仅在设计中纳入合法的布局和路线; 并应用增量时间来评估变革，并更新现有的时间图，以反映由法定刊登位置和路线组成的变更。

公开(公告)号：US20120317527A1

公开(公告)日：2012-12-13

申请号：US13590115

申请日：2012-08-20

申请人： Michael D. Moffitt ,  Matyas A. Sustik ,  Paul G. Villarrubia

发明人： Michael D. Moffitt ,  Matyas A. Sustik ,  Paul G. Villarrubia

IPC分类号： G06F17/50

CPC分类号： G06F17/5027

摘要： A circuit design is partitioned for hardware-accelerated functional verification using a directed hypergraph with edge weights that are a function of slack. Slack may be computed as the difference between the early and late ranks for the source of an edge. The weight may further be computed as the difference between the edge's slack and a maximum slack value. In a preferred implementation each vertex also has multiple weights associated with resource requirements of different node types, and the partitioning is constrained to prevent vertex movement that would result in vertex weights for a given partition exceeding a partition resource capacity based on the accelerator architecture. Edge and vertex weights can be recomputed for the next level of partitioning. The partitioning process can be repeatedly iteratively until a termination criterion is met, the termination criterion being based in part on the number of directed cuts in each of the partitions.

摘要翻译： 使用具有作为松弛功能的边缘权重的定向超图来对电路设计进行硬件加速功能验证。 松弛可以计算为边缘来源的早期和晚期等级之间的差异。 重量可以进一步计算为边缘的松弛和最大松弛值之间的差。 在优选实施例中，每个顶点还具有与不同节点类型的资源需求相关联的多个权重，并且限制划分以防止顶点移动，其将导致基于加速器架构的给定分区的顶点权重超过分区资源容量。 边缘和顶点权重可以重新计算下一级分区。 分区过程可以重复迭代直到满足终止标准，终止标准部分地基于每个分区中的定向切割的数量。

公开(公告)号：US08245173B2

公开(公告)日：2012-08-14

申请号：US12359369

申请日：2009-01-26

申请人： Gi-Joon Nam ,  Shyam Ramji ,  Taraneh Taghavi ,  Paul G. Villarrubia

发明人： Gi-Joon Nam ,  Shyam Ramji ,  Taraneh Taghavi ,  Paul G. Villarrubia

IPC分类号： G06F17/50

CPC分类号： G06F17/50 ,  G06F9/5066

摘要： Scheduling of parallel processing for regionally-constrained object placement selects between different balancing schemes. For a small number of movebounds, computations are assigned by balancing the placeable objects. For a small number of objects per movebound, computations are assigned by balancing the movebounds. If there are large numbers of movebounds and objects per movebound, both objects and movebounds are balanced amongst the processors. For object balancing, movebounds are assigned to a processor until an amortized number of objects for the processor exceeds a first limit above an ideal number, or the next movebound would raise the amortized number of objects above a second, greater limit. For object and movebound balancing, movebounds are sorted into descending order, then assigned in the descending order to host processors in successive rounds while reversing the processor order after each round. The invention provides a schedule in polynomial-time while retaining high quality of results.

摘要翻译： 区域约束对象放置的并行处理调度在不同的平衡方案之间进行选择。 对于少量的移动端口，通过平衡可放置对象来分配计算。 对于每次移动的少量对象，通过平衡移动端口分配计算。 如果每次移动都有大量的移动和对象，则处理器之间的对象和移动对象都是平衡的。 对于对象平衡，移动端口被分配给一个处理器，直到处理器的对象的摊销数量超过理想数量以上的第一个限制，或者下一个移动端口将提高超过第二个更大限制的对象数量。 对于对象和移动平衡，移动排列按降序排列，然后按顺序分配给主机处理器，连续回合，同时在每轮之后反转处理器顺序。 本发明提供多项式时间的时间表，同时保持高质量的结果。