Display panel and display device
    11.
    发明授权

    公开(公告)号:US12020642B2

    公开(公告)日:2024-06-25

    申请号:US17771073

    申请日:2021-02-19

    CPC classification number: G09G3/3233

    Abstract: This disclosure provides a display panel and a display device. The display panel includes a light-transmitting area, a first transitional display area, a first main display area and a second main display area, and further includes a first light-emitting unit in the light-transmitting area, a first pixel driving circuit in the first transitional display area for providing a driving current to the first light-emitting unit, a first signal line extending along the column direction in the first main display area, a second signal line extending along the column direction in the second main display area, and a third signal line. The third signal line and the first signal line are in different conductive layers, the third signal line and the second signal line are in different conductive layers, and the third signal line is connected with the first signal line and the second signal line through via holes respectively.

    Method for preparing array substrate

    公开(公告)号:US11251207B2

    公开(公告)日:2022-02-15

    申请号:US16846888

    申请日:2020-04-13

    Abstract: The present disclosure discloses a method for preparing an array substrate, an array substrate and a display panel, wherein the method comprises: forming a buffer layer on a substrate in a first region and a second region, wherein the buffer layer has a groove located in the second region; forming a first indium oxide thin film on the buffer layer in the first region; forming a second indium oxide thin film in the groove; performing a reduction process on the second indium oxide thin film to obtain indium particles; forming an amorphous silicon thin film in the groove, and inducing the amorphous silicon of the amorphous silicon thin film to form microcrystalline silicon at a preset temperature by using the indium particles; and removing the indium particles in the microcrystalline silicon to form a microcrystalline silicon semiconductor layer of the microcrystalline silicon thin film transistor.

    Oxide thin film transistor, array substrate, and preparation methods thereof

    公开(公告)号:US20200185535A1

    公开(公告)日:2020-06-11

    申请号:US16528622

    申请日:2019-08-01

    Abstract: An oxide thin film transistor, an array substrate, and preparation methods thereof are disclosed. The method for preparing an oxide thin film transistor comprises a step of forming a pattern comprising an oxide semiconductor active layer on a substrate, wherein the step comprises: forming an amorphous oxide semiconductor thin film on the substrate; performing an excimer laser annealing, at least at a position in the amorphous oxide semiconductor thin film corresponding to a channel region of oxide semiconductor active layer to be formed, such that the amorphous oxide semiconductor material at the laser-annealed position is crystallized, to form a crystalline oxide semiconductor material; and forming the pattern comprising the oxide semiconductor active layer.

    Display panel, display apparatus and manufacturing method thereof

    公开(公告)号:US12150352B2

    公开(公告)日:2024-11-19

    申请号:US17425198

    申请日:2020-09-24

    Abstract: A display panel, a display apparatus, a manufacturing method of the display panel are provided. The display panel includes a light-transmitting area including: a first light-transmitting area with multiple light-emitting units distributed at intervals; a second light-transmitting area with multiple light-emitting driving units capable of transmitting light. The first light-transmitting area is connected with the second light-transmitting area; each light-emitting unit is connected with a light-emitting driving unit, the light-emitting driving units are configured to drive the connected light-emitting units to emit light; some light-emitting units are connected with the light-emitting driving units through first connecting wires in the light-transmitting area, some light-emitting units are connected with the light-emitting driving units through second connecting wires outside the light-transmitting area; the second connecting wires are along an edge of the light-transmitting area.

    Pixel circuit, driving method for same, and display apparatus

    公开(公告)号:US11810506B2

    公开(公告)日:2023-11-07

    申请号:US17608746

    申请日:2021-02-10

    Abstract: A pixel circuit, driving method for same and display apparatus are provided. The pixel circuit includes a driving sub-circuit, writing sub-circuit, compensation sub-circuit, first reset sub-circuit, first and second emitting control sub-circuits, and emitting element. The compensation sub-circuit writes signal of third node into first node under control of third scanning signal terminal, and compensates first node under control of the third scanning signal terminal and first voltage terminal. The first reset sub-circuit writes signal of first initial signal terminal into third node under control of first scanning signal terminal and first emitting control signal terminal. The second emitting control sub-circuit provides signal of first voltage terminal for second node under control of second emitting control signal terminal. The first emitting control sub-circuit provides signal of third node for fourth node under control of the first emitting control signal terminal, allows driving current to flow between third and fourth nodes.

    Thin film transistor and method for manufacturing a thin film transistor

    公开(公告)号:US11309427B2

    公开(公告)日:2022-04-19

    申请号:US16642638

    申请日:2019-03-04

    Abstract: The present disclosure relates to a thin film transistor and a manufacturing method thereof. The thin film transistor includes a substrate, a first semiconductor layer, a gate dielectric layer, and a gate electrode sequentially stacked on the substrate, the first semiconductor layer has a first portion located in a channel region of the thin film transistor and a second portion in source/drain regions of the thin film transistor and located on both sides of the first portion, the second portion and first sub-portions of the first portion adjacent to the second portion include an amorphous semiconductor material, a second sub-portion of the first portion between the first sub-portions includes a polycrystalline semiconductor material, and a second semiconductor layer located in the source/drain regions and in contact with the second portion, wherein a conductivity of the second semiconductor layer is higher than a conductivity of the amorphous semiconductor material.

    Shift register unit and method for driving the same, gate driving circuit and display apparatus

    公开(公告)号:US11282469B2

    公开(公告)日:2022-03-22

    申请号:US16640726

    申请日:2019-09-23

    Abstract: The embodiments of the present disclosure disclose a shift register unit and a method for driving the same, a gate driving circuit, and a display apparatus. The shift register unit includes: an input circuit configured to output an input signal from an input signal terminal to a pull-up node; an output circuit configured to output a clock signal from a clock signal terminal to an output signal terminal under control of a potential at the pull-up node; a resetting and de-noising circuit configured to reset and de-noise the pull-up node and the output signal terminal under control of a potential at a pull-down node; and a pull-down node control circuit coupled to a first voltage terminal and the pull-down node, and configured to electrically couple the pull-down node to the first voltage terminal under control of the potential at the pull-down node.

    CMOS structure and method for manufacturing CMOS structure

    公开(公告)号:US11264384B2

    公开(公告)日:2022-03-01

    申请号:US16642723

    申请日:2019-03-04

    Abstract: The disclosure relates to a CMOS structure and a manufacturing method thereof. The CMOS structure includes a substrate and an N-type TFT and a P-type TFT on the substrate. The N-type TFT includes a first gate electrode, a first active layer, and a first gate dielectric layer therebetween. The first active layer includes a first semiconductor layer, a second semiconductor layer of the N-type, and a third semiconductor layer of the N-type which are located at opposite ends of the first semiconductor layer and sequentially stacked in a direction away from the first gate dielectric layer. An N-type doping concentration of the second semiconductor layer is smaller than that of the third semiconductor layer. The P-type TFT includes a fifth semiconductor layer and a sixth semiconductor layer. A P-type doping concentration of the fifth semiconductor layer is smaller than that of the sixth semiconductor layer.

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