公开(公告)号：US11763729B2

公开(公告)日：2023-09-19

申请号：US17638123

申请日：2021-01-22

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xitong Ma ,  Lihua Geng ,  Congrui Wu

IPC: G09G5/12 ,  G09G3/294

CPC classification number: G09G3/2946 ,  G09G5/12 ,  G09G2320/0693

Abstract: A method includes: obtaining a first frame synchronization signal, period between a trailing edge of a first pulse and a leading edge of a next first pulse being first time period corresponding to a first integer number of pulses of a first pixel clock signal; generating a synchronization calibration signal, a triggering edge of the second pulse being delayed compared to a trailing edge of a first pulse; generating a second frame synchronization signal, period between a triggering edge of the second pulse and a leading edge of a third pulse being second time period. When ratio of frequency of the second pixel clock signal to frequency of the first pixel clock signal is within threshold range, the second time period corresponds to a second integer number of pulses of the second pixel clock signal. The second integer is integer value of product of the first integer and ratio.

公开(公告)号：US11563989B2

公开(公告)日：2023-01-24

申请号：US17331209

申请日：2021-05-26

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xitong Ma ,  Lihua Geng ,  Congrui Wu ,  Yanfu Li ,  Xian Wang

IPC: H04N21/2365 ,  G06F13/40 ,  G11B27/32 ,  H04N21/23 ,  H04N21/2368 ,  H04N21/236

Abstract: A signal processing device is disclosed, which includes a plurality of channel receivers, a plurality of time code processors in one-to-one correspondence with the channel receivers, a timing generator, a signal processor and a transmitter, wherein each channel receiver is configured to parse an audio-video signal which has a data format defined by the SDI protocol and including a time code that characterizes time information. Each time code processor is configured to extract the time code from a parsed audio-video signal obtained by a corresponding channel receiver, and form first frame image data including a frame time code. The signal processor is configured to form an absolute frame output image based on multiple channels of the first frame of image data, frame time codes therein, and an internal clock signal generated by the timing generator. The transmitter is configured to transmit the absolute frame output image for display.

公开(公告)号：US11349650B2

公开(公告)日：2022-05-31

申请号：US16960053

申请日：2019-12-16

Applicant: BOE Technology Group Co., Ltd.

Inventor： Congrui Wu

IPC: H04L9/08 ,  H04L9/06 ,  G11C7/22

Abstract: A circuit for data encryption is provided. The circuit includes an encryption controller configured to randomly generate a frequency parameter defining different timeframes corresponding to different frequencies. The circuit also includes a random-clock-signal generator configured to receive the frequency parameter to synthesize an encryption clock signal based on a base clock signal. The encryption clock signal includes a random combination of different clock frequencies respectively over multiple different timeframes. Additionally, the circuit includes an encryption sub-circuit configured to receive plain data and to encrypt the plain data by a sampling replacement driven by the encryption clock signal to obtain encrypted data.

公开(公告)号：US20210250170A1

公开(公告)日：2021-08-12

申请号：US16960053

申请日：2019-12-16

Applicant: BOE Technology Group Co., Ltd.

Inventor： Congrui Wu

IPC: H04L9/08 ,  H04L9/06 ,  G06F13/40 ,  G06F13/38 ,  G06F13/42

Abstract: A circuit for data encryption is provided. The circuit includes an encryption controller configured to randomly generate a frequency parameter defining different timeframes corresponding to different frequencies. The circuit also includes a random-clock-signal generator configured to receive the frequency parameter to synthesize an encryption clock signal based on a base clock signal. The encryption clock signal includes a random combination of different clock frequencies respectively over multiple different timeframes. Additionally, the circuit includes an encryption sub-circuit configured to receive plain data and to encrypt the plain data by a sampling replacement driven by the encryption clock signal to obtain encrypted data.