公开(公告)号：US20040036644A1

公开(公告)日：2004-02-26

申请号：US10226165

申请日：2002-08-23

Applicant: Broadcom Corporation

Inventor： Jan Mulder ,  Franciscus M. L. van der Goes

IPC: H03M001/34 ,  H03K005/00

CPC classification number: H03M1/0863 ,  H03M1/36

Abstract: A method for reducing bit errors in an analog to digital converter having an array of comparators. The outputs of first and second comparators are received as in inputs to an Exclusive OR gate. The first and second comparators are separated in the array by a third comparator. The output of the Exclusive OR gate is used to determine if the third comparator is in a metastable condition. If the third comparator is in a metastable condition, the bias current of the latch circuit of the third comparator is increased to increase the rate at which the third comparator transitions to a steady state.

Abstract translation: 一种用于减少具有比较器阵列的模数转换器中的位错误的方法。 第一和第二比较器的输出如在异或门的输入中一样被接收。 第一和第二比较器由阵列中的第三比较器分开。 异或门的输出用于确定第三比较器是否处于亚稳态。 如果第三比较器处于亚稳态，则第三比较器的锁存电路的偏置电流增加，以增加第三比较器转变到稳定状态的速率。