公开(公告)号：US20040140830A1

公开(公告)日：2004-07-22

申请号：US10720144

申请日：2003-11-25

Applicant: Broadcom Corporation

Inventor： Jan Mulder ,  Yee Ling Cheung

IPC: H03K005/22

CPC classification number: H03K17/04106 ,  H03M1/146 ,  H03M1/204 ,  H03M1/365 ,  H03M1/742 ,  H04L25/026 ,  H04L25/0276

Abstract: A differential line driver includes first, second, third and fourth cascode transistors connected in parallel, wherein drains of the first and third transistors are connected to a negative output of the differential line driver, and wherein drains of the second and fourth transistors are connected to a positive output of the differential line driver. First, second, third and fourth switching transistors are connected in series with corresponding first, second, third and fourth cascode transistors and driven by a data signal. First and second compound transistors inputting a class AB operation signal at their gates, wherein the first compound transistor is connected to sources of the first and second switching transistors, and wherein the second compound transistor is connected to sources of the third and fourth switching transistors.

Abstract translation: 差分线路驱动器包括并联连接的第一，第二，第三和第四共源共栅晶体管，其中第一和第三晶体管的漏极连接到差分线路驱动器的负输出，并且其中第二和第四晶体管的漏极连接到 差分线路驱动器的正输出。 第一，第二，第三和第四开关晶体管与对应的第一，第二，第三和第四共源共栅晶体管串联连接并由数据信号驱动。 第一和第二复合晶体管在其栅极处输入AB类操作信号，其中第一复合晶体管连接到第一和第二开关晶体管的源极，并且其中第二复合晶体管连接到第三和第四开关晶体管的源极。

公开(公告)号：US20030218560A1

公开(公告)日：2003-11-27

申请号：US10460622

申请日：2003-06-13

Applicant: Broadcom Corporation

Inventor： Jan Mulder ,  Christopher Michael Ward

IPC: H03M001/36

CPC classification number: H03K17/04106 ,  H03M1/0646 ,  H03M1/146 ,  H03M1/204 ,  H03M1/206 ,  H03M1/361 ,  H03M1/365

Abstract: An analog to digital converter includes a first amplifier array connected to taps from a reference ladder, a second amplifier array, wherein each amplifier in the first amplifier array is connected to only two amplifiers of the second amplifier array, a third amplifier array, wherein each amplifier in the second amplifier array is connected to only two amplifiers of the third amplifier array, and an encoder connected to outputs of the third amplifier array that converts the outputs to an N-bit digital signal.

Abstract translation: 模数转换器包括连接到参考梯形图的抽头的第一放大器阵列，第二放大器阵列，其中第一放大器阵列中的每个放大器仅连接到第二放大器阵列的两个放大器，第三放大器阵列，其中每个 第二放大器阵列中的放大器仅连接到第三放大器阵列的两个放大器，以及连接到第三放大器阵列的输出的编码器，其将输出转换为N位数字信号。

公开(公告)号：US20030218556A1

公开(公告)日：2003-11-27

申请号：US10359201

申请日：2003-02-06

Applicant: Broadcom Corporation

Inventor： Franciscus Maria Leonardus van der Goes ,  Jan Mulder ,  Christopher Michael Ward ,  Jan Roelof Westra ,  Rudy van de Plassche ,  Marcel Lugthart

IPC: H03M001/12

CPC classification number: H03M1/146 ,  H03K17/04106 ,  H03M1/204 ,  H03M1/365

Abstract: An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.

Abstract translation: N位模数转换器包括参考梯形图，连接到输入电压的跟踪和保持放大器，在其输入处连接到粗略电容器的粗略ADC放大器，并具有由第一时钟控制的粗略ADC复位开关 两相时钟的相位，精细ADC放大器在其输入端连接到精细电容器，并具有由两相时钟的第二时钟相位控制的精细ADC复位开关，开关矩阵从第二时钟相位选择电压子范围 参考梯形图，用于基于粗ADC放大器的输出的精细ADC放大器使用，并且其中粗电容器在第一时钟相位期间被充电到粗略的参考梯形电压，并且在第二时钟相位期间连接到T / H输出 其中精细电容器在第一时钟相位期间连接到电压子范围，并且在第二时钟相位期间连接到T / H输出;以及编码器，其将粗略和精细ADC放大器的输出转换为Nb 它输出。

公开(公告)号：US20040164770A1

公开(公告)日：2004-08-26

申请号：US10791878

申请日：2004-03-04

Applicant: Broadcom Corporation

Inventor： Jan Mulder ,  Marcel Lugthart ,  Chi-Hung Lin

IPC: H03D001/00

CPC classification number: H03H11/32

Abstract: Provided is a circuit to perform single-ended to differential conversion while providing common-mode voltage control. The circuit includes a converter to convert a single-ended signal to a differential signal and a stabilizing circuit adapted to receive the differential signal. The stabilizing circuit includes a sensor configured to sense a common-mode voltage level of the differential signal and a comparator having an output port coupled to the converter. The comparator is configured to compare the differential signal common-mode voltage level with a reference signal common-mode voltage level and produce an adjusting signal based upon the comparison. The adjusting signal is applied to the converter via the output port and is operative to adjust a subsequent common-mode voltage level of the differential signal.

公开(公告)号：US20040155807A1

公开(公告)日：2004-08-12

申请号：US10625702

申请日：2003-07-24

Applicant: Broadcom Corporation

Inventor： Franciscus Maria Leonardus van der Goes ,  Jan Mulder ,  Christopher Michael Ward ,  Jan Roelof Westra ,  Rudy van de Plassche ,  Marcel Lugthart

IPC: H03M001/12

CPC classification number: H03M1/146 ,  H03K17/04106 ,  H03M1/204 ,  H03M1/365

Abstract: An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output ofthe coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.

Abstract translation: N位模数转换器包括参考梯形图，连接到输入电压的跟踪和保持放大器，在其输入处连接到粗略电容器的粗略ADC放大器，并具有由第一时钟控制的粗略ADC复位开关 两相时钟的相位，精细ADC放大器在其输入端连接到精细电容器，并具有由两相时钟的第二时钟相位控制的精细ADC复位开关，开关矩阵从第二时钟相位选择电压子范围 基准梯形图，其基于粗略ADC放大器的输出由精细ADC放大器使用，并且其中粗电容器在第一时钟相位期间被充电到粗略的参考梯形电压，并且在第二时钟相位期间连接到T / H输出， 其中精细电容器在第一时钟相位期间连接到电压子范围，在第二时钟相位期间连接到T / H输出;以及编码器，其将粗略和精细ADC放大器的输出转换为N-bi t输出。

公开(公告)号：US20040257255A1

公开(公告)日：2004-12-23

申请号：US10893999

申请日：2004-07-20

Applicant: Broadcom Corporation

Inventor： Jan Mulder

IPC: H03M001/12

CPC classification number: H03M1/0863 ,  H03K17/04106 ,  H03M1/146 ,  H03M1/204 ,  H03M1/36 ,  H03M1/365

Abstract: An input stage includes a plurality of arrays of autozero amplifiers arranged in series in each array, wherein each autozero amplifier receives an output of a preceding autozero amplifier, wherein a first autozero amplifier in each array amplifiers receives an input signal and a corresponding reference voltage at its inputs, and wherein at least one of the autozero amplifiers includes a circuit that receives the signal corresponding to the output signal, the circuit substantially passing the signal corresponding to the output signal and the reference voltages to the amplifiers during the clock phase null2 and substantially rejecting the signal corresponding to the output signal during the clock phase null1.

Abstract translation: 输入级包括在每个阵列中串联布置的多个自动调零放大器阵列，其中每个自动调零放大器接收前一自动调零放大器的输出，其中每个阵列放大器中的第一自动调零放大器接收输入信号和对应的参考电压 其输入，并且其中至少一个自动调零放大器包括接收对应于输出信号的信号的电路，该电路在时钟相位phi2期间基本上将对应于输出信号的信号和参考电压传送到放大器，并且基本上 在时钟相位phi1期间拒绝对应于输出信号的信号。

公开(公告)号：US20040041611A1

公开(公告)日：2004-03-04

申请号：US10649808

申请日：2003-08-28

Applicant: Broadcom Corporation

Inventor： Klaas Bult ,  Rudy Van de Plassche ,  Jan Mulder

IPC: H03K003/037

CPC classification number: H03K3/356043 ,  H03K3/012 ,  H03K3/35613 ,  H03K3/356182 ,  H03K3/356191 ,  H03M1/002 ,  H03M1/362

Abstract: In a latch circuit having a bistable pair of cross connected transistors of a first polarity and a third transistor of a second polarity, a current signal greater than a bias current is received at a latch circuit port, amplified with the third transistor, and applied to the latch circuit port. This decreases the time in which the latch circuit port receiving the current signal greater than the bias current reaches a steady state voltage.

Abstract translation: 在具有第一极性的双稳态交叉晶体管对和第二极性的第三晶体管的锁存电路中，在锁存电路端口处接收大于偏置电流的电流信号，用第三晶体管放大并施加到 锁存电路端口。 这减小了接收大于偏置电流的电流信号的锁存电路端口达到稳态电压的时间。

公开(公告)号：US20040150544A1

公开(公告)日：2004-08-05

申请号：US10748250

申请日：2003-12-31

Applicant: Broadcom Corporation

Inventor： Jan Mulder

IPC: H03M001/36

CPC classification number: H03K17/04106 ,  H03M1/146 ,  H03M1/204 ,  H03M1/365 ,  H04L25/026 ,  H04L25/0276

Abstract: An N-bit analog to digital converter includes a reference ladder connected to an input voltage at one end, and to ground at another end, an array of differential amplifiers whose differential inputs are connected to taps from the reference ladder, wherein each amplifier has a first differential input connected to the same tap as a neighboring amplifier, and a second differential input shifted by one tap from the neighboring amplifier, and an encoder that converts outputs of the array to an N-bit output.

Abstract translation: N位模数转换器包括连接到一端的输入电压并在另一端接地的参考梯形图，其差分放大器的阵列与差分输入端连接到来自参考梯形图的抽头，其中每个放大器具有 连接到与相邻放大器相同的抽头的第一差分输入和从相邻放大器偏移一抽头的第二差分输入，以及将阵列的输出转换为N位输出的编码器。

公开(公告)号：US20040085235A1

公开(公告)日：2004-05-06

申请号：US10688921

申请日：2003-10-21

Applicant: Broadcom Corporation

Inventor： Jan Mulder

IPC: H03M001/34

CPC classification number: H03M1/0863 ,  H03K17/04106 ,  H03M1/146 ,  H03M1/204 ,  H03M1/36 ,  H03M1/365

Abstract: An analog to digital converter includes a reference ladder, a track-and-hold amplifier tracking an input signal with its output signal during the phase null1 and holding a sampled value during, a coarse analog to digital converter having a plurality of coarse amplifiers each inputting a corresponding tap from the reference ladder and the output signal, a fine analog-to-digital converter having a plurality of fine amplifiers inputting corresponding taps from the reference ladder and the output signal, the taps selected based on outputs of the coarse amplifiers, a clock having phases null1 and null2, a circuit responsive to the clock that receives the output signal, the circuit substantially passing the output signal and the corresponding taps to the fine amplifiers during the phase null2 and substantially rejecting the output signal and the corresponding taps during the phase null1, and an encoder converting outputs of the coarse and fine amplifiers to an N-bit digital signal representing the input signal.

公开(公告)号：US20040080443A1

公开(公告)日：2004-04-29

申请号：US10684444

申请日：2003-10-15

Applicant: Broadcom Corporation

Inventor： Jan Mulder ,  Christopher Michael Ward

IPC: H03M001/34

CPC classification number: H03K17/04106 ,  H03M1/0646 ,  H03M1/146 ,  H03M1/204 ,  H03M1/206 ,  H03M1/361 ,  H03M1/365

Abstract: An analog to digital converter includes a first amplifier array connected to taps from a reference ladder, a second amplifier array, wherein each amplifier in the first amplifier array is connected to only two amplifiers of the second amplifier array, a third amplifier array, wherein each amplifier in the second amplifier array is connected to only two amplifiers of the third amplifier array, and an encoder connected to outputs of the third amplifier array that converts the outputs to an N-bit digital signal.