公开(公告)号：US08383480B1

公开(公告)日：2013-02-26

申请号：US13295191

申请日：2011-11-14

Applicant: Chih-Ming Wang ,  Ping-Chia Shih ,  Chi-Cheng Huang ,  Hsiang-Chen Lee ,  Chih-Hung Lin

Inventor： Chih-Ming Wang ,  Ping-Chia Shih ,  Chi-Cheng Huang ,  Hsiang-Chen Lee ,  Chih-Hung Lin

IPC: H01L21/336

CPC classification number: H01L29/4234 ,  H01L21/28282 ,  H01L29/66833 ,  H01L29/792

Abstract: A method for forming a semiconductor structure includes following steps. A substrate structure is provided. The substrate structure includes a semiconductor substrate, a first oxide-nitride-oxide (ONO) layer, and a second ONO layer. The semiconductor substrate has first and second surfaces opposite to each other. The first ONO layer includes a first oxide layer, a first nitride layer and a second oxide layer formed on the first surface in sequence. The second ONO layer includes a third oxide layer, a second nitride layer and a fourth oxide layer formed on the second surface in sequence. A nitride mask layer is formed on the first ONO layer. The fourth oxide layer is removed. The second nitride layer and the nitride mask layer are removed. The second oxide layer and the third oxide layer are removed. A fifth oxide layer is formed on the first nitride layer.

Abstract translation: 一种形成半导体结构的方法包括以下步骤。 提供了基板结构。 衬底结构包括半导体衬底，第一氧化物 - 氧化物 - 氧化物（ONO）层和第二ONO层。 半导体衬底具有彼此相对的第一和第二表面。 第一ONO层包括顺序地形成在第一表面上的第一氧化物层，第一氮化物层和第二氧化物层。 第二ONO层包括依次形成在第二表面上的第三氧化物层，第二氮化物层和第四氧化物层。 在第一ONO层上形成氮化物掩模层。 去除第四氧化物层。 去除第二氮化物层和氮化物掩模层。 去除第二氧化物层和第三氧化物层。 在第一氮化物层上形成第五氧化物层。

公开(公告)号：US08546226B2

公开(公告)日：2013-10-01

申请号：US13189632

申请日：2011-07-25

Applicant: Chih-Ming Wang ,  Ping-Chia Shih ,  Chun-Sung Huang ,  Chi-Cheng Huang ,  Hsiang-Chen Lee ,  Chih-Hung Lin ,  Yau-Kae Sheu

Inventor： Chih-Ming Wang ,  Ping-Chia Shih ,  Chun-Sung Huang ,  Chi-Cheng Huang ,  Hsiang-Chen Lee ,  Chih-Hung Lin ,  Yau-Kae Sheu

IPC: H01L21/336 ,  H01L29/792

CPC classification number: H01L21/28282 ,  H01L29/792

Abstract: A method for fabricating a silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory cell, wherein the method comprises steps as following: a pad oxide layer and a first hard mask layer are sequentially formed on a substrate. The pad oxide layer and the first hard mask layer are then etched through to form an opening exposing a portion of the substrate. Subsequently, an oxide-nitride-oxide (ONO) structure with a size substantially less than or equal to the opening is formed to coincide with the portion of the substrate exposed from the opening.

Abstract translation: 一种用于制造氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）非易失性存储单元的方法，其中该方法包括以下步骤：在衬底上依次形成衬垫氧化物层和第一硬掩模层。 然后将衬垫氧化物层和第一硬掩模层蚀刻通过以形成露出衬底的一部分的开口。 随后，形成具有基本上小于或等于该开口的尺寸的氧化物 - 氧化物 - 氧化物（ONO）结构，以与从该开口露出的该基板的一部分重合。

公开(公告)号：US08222112B2

公开(公告)日：2012-07-17

申请号：US13114045

申请日：2011-05-24

Applicant: Chun-Sung Huang ,  Ping-Chia Shih ,  Chiao-Lin Yang ,  Chi-Cheng Huang

Inventor： Chun-Sung Huang ,  Ping-Chia Shih ,  Chiao-Lin Yang ,  Chi-Cheng Huang

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L27/11568 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/66833

Abstract: A method for manufacturing NAND memory cells includes providing a substrate having a first doped region formed therein; forming a first dielectric layer, a storage layer and a patterned hard mask on the substrate; forming a STI in the substrate through the patterned hard mask and removing the patterned hard mask to define a plurality of recesses; forming a second dielectric layer and a first conductive layer filling the recesses on the substrate; and performing a planarization process to remove a portion of the first conductive layer and the second dielectric layer to form a plurality of self-aligned islanding gate structures.

Abstract translation: 一种用于制造NAND存储器单元的方法包括提供其中形成有第一掺杂区的衬底; 在基板上形成第一电介质层，存储层和图案化的硬掩模; 通过图案化的硬掩模在衬底中形成STI，并去除图案化的硬掩模以限定多个凹槽; 形成第二电介质层和填充所述基板上的所述凹部的第一导电层; 以及执行平坦化处理以去除所述第一导电层和所述第二介电层的一部分以形成多个自对准岛状栅极结构。

公开(公告)号：US20110220988A1

公开(公告)日：2011-09-15

申请号：US13114045

申请日：2011-05-24

Applicant: Chun-Sung Huang ,  Ping-Chia Shih ,  Chiao-Lin Yang ,  Chi-Cheng Huang

Inventor： Chun-Sung Huang ,  Ping-Chia Shih ,  Chiao-Lin Yang ,  Chi-Cheng Huang

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L27/11568 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/66833

Abstract: A method for manufacturing NAND memory cells includes providing a substrate having a first doped region formed therein; forming a first dielectric layer, a storage layer and a patterned hard mask on the substrate; forming a STI in the substrate through the patterned hard mask and removing the patterned hard mask to define a plurality of recesses; forming a second dielectric layer and a first conductive layer filling the recesses on the substrate; and performing a planarization process to remove a portion of the first conductive layer and the second dielectric layer to form a plurality of self-aligned islanding gate structures.

Abstract translation: 一种用于制造NAND存储器单元的方法包括提供其中形成有第一掺杂区的衬底; 在基板上形成第一电介质层，存储层和图案化的硬掩模; 通过图案化的硬掩模在衬底中形成STI，并去除图案化的硬掩模以限定多个凹槽; 形成第二电介质层和填充所述基板上的所述凹部的第一导电层; 以及执行平坦化处理以去除所述第一导电层和所述第二介电层的一部分以形成多个自对准岛状栅极结构。

公开(公告)号：US20090262025A1

公开(公告)日：2009-10-22

申请号：US12166086

申请日：2008-07-01

Applicant: Chi-Cheng Huang

Inventor： Chi-Cheng Huang

IPC: H01Q9/04

CPC classification number: H01Q9/0421 ,  H01Q9/36 ,  H01Q9/40 ,  H01Q9/42

Abstract: An antenna and an antenna set are provided. The antenna is composed of a horseshoe sheet member and two rectangular sheet members. The horseshoe sheet member and the two rectangular sheet members are all made of a metal material. The antenna is made of a metal material, such as tinplate, and the antenna is adapted for receiving or emitting wireless signals of vertical polarization and horizontal polarization. The antenna set includes three antennae as above disposed on a substrate. The antenna set is adapted for polarization diversity, pattern diversity, and space diversity. Comparing with the conventional antenna and antenna set, the antenna and the antenna set according to the present invention have lower costs and lower heights, and can be designed as embedded antennae or hidden antennae.

Abstract translation: 提供天线和天线组。 天线由马蹄片构件和两个矩形片构件组成。 马蹄板构件和两个矩形片构件均由金属材料制成。 天线由诸如马口铁的金属材料制成，天线适于接收或发射垂直极化和水平极化的无线信号。 天线组包括如上设置在基板上的三个天线。 天线组适用于极化分集，模式分集和空间分集。 与传统天线和天线组相比，根据本发明的天线和天线组具有较低的成本和较低的高度，并且可以被设计为嵌入式天线或隐藏天线。