公开(公告)号：US20100153601A1

公开(公告)日：2010-06-17

申请号：US12402635

申请日：2009-03-12

Applicant: Hao-Lin Lin

Inventor： Hao-Lin Lin

IPC: G06F13/00

CPC classification number: G06F13/376

Abstract: A computer system is provided. The computer system includes a bus, a first master device, a second master device and a processor. The bus has a data line and a clock line. The first master device is coupled to the bus, detects a start phase of a first transaction on the data line, issues an interrupt message upon the detection of the start phase, and triggers a second transaction in response to a transaction indication message. The processor is coupled to the first master device, receives the interrupt message, and transmits the transaction indication message after a predetermined time interval upon reception of the interrupt message. The second master device is coupled to the bus and triggers the first transaction. The first transaction is finished within the predetermined time interval.

Abstract translation: 提供计算机系统。 计算机系统包括总线，第一主设备，第二主设备和处理器。 总线有数据线和时钟线。 第一主设备耦合到总线，检测数据线上的第一事务的起始阶段，在检测到起始阶段时发出中断消息，并响应于事务指示消息触发第二事务。 处理器耦合到第一主设备，接收中断消息，并且在接收到中断消息之后在预定时间间隔之后发送交易指示消息。 第二主设备耦合到总线并触发第一事务。 第一个事务在预定的时间间隔内完成。

公开(公告)号：US07882290B2

公开(公告)日：2011-02-01

申请号：US12402635

申请日：2009-03-12

Applicant: Hao-Lin Lin

Inventor： Hao-Lin Lin

IPC: G06F13/00 ,  G06F13/372

CPC classification number: G06F13/376

Abstract: A computer system is provided. The computer system includes a bus, a first master device, a second master device and a processor. The bus has a data line and a clock line. The first master device is coupled to the bus, detects a start phase of a first transaction on the data line, issues an interrupt message upon the detection of the start phase, and triggers a second transaction in response to a transaction indication message. The processor is coupled to the first master device, receives the interrupt message, and transmits the transaction indication message after a predetermined time interval upon reception of the interrupt message. The second master device is coupled to the bus and triggers the first transaction. The first transaction is finished within the predetermined time interval.

Abstract translation: 提供计算机系统。 计算机系统包括总线，第一主设备，第二主设备和处理器。 总线有数据线和时钟线。 第一主设备耦合到总线，检测数据线上的第一事务的起始阶段，在检测到起始阶段时发出中断消息，并响应于事务指示消息触发第二事务。 处理器耦合到第一主设备，接收中断消息，并且在接收到中断消息之后在预定时间间隔之后发送交易指示消息。 第二主设备耦合到总线并触发第一事务。 第一个事务在预定的时间间隔内完成。

公开(公告)号：US20080114977A1

公开(公告)日：2008-05-15

申请号：US11861335

申请日：2007-09-26

Applicant: Hao-Lin Lin ,  Hsiao-Fung Chou

Inventor： Hao-Lin Lin ,  Hsiao-Fung Chou

IPC: G06F15/177

CPC classification number: G06F13/4072

Abstract: An embodiment of a computer system comprises a south-bridge. The south-bridge comprises a controller including a buffer for communicating with electronic devices. When detecting that a Reset# signal is asserted, the buffer is set to a Hi-Impedance state to separate the controller from the electronic device. The Reset# signal indicates a full system reset.

Abstract translation: 计算机系统的一个实施例包括一个南桥。 南桥包括一个包括与电子设备进行通信的缓冲器的控制器。 当检测到Reset＃信号被断言时，缓冲器被设置为Hi-Impedance状态以将控制器与电子设备分离。 Reset＃信号表示完整的系统复位。