公开(公告)号：US06825523B2

公开(公告)日：2004-11-30

申请号：US10267033

申请日：2002-10-07

申请人： Paolo Caprara ,  Claudio Brambilla ,  Manlio Sergio Cereda

发明人： Paolo Caprara ,  Claudio Brambilla ,  Manlio Sergio Cereda

IPC分类号： H01L2976

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/792 ,  H01L29/7923

摘要： A process for manufacturing a dual charge storage location electrically programmable memory cell that includes the steps of forming a central insulated gate over a semiconductor substrate; forming physically separated charge-confining layers stack portions of a dielectric-charge trapping material-dielectric layers stack at the sides of the central gate, the charge trapping material layer in each charge-confining layers stack portion forming a charge storage element; forming side control gates over each of the charge-confining layers stack portions; forming memory cell source/drain regions laterally to the side control gates; and electrically connecting the side control gates to the central gate. Each of the charge-confining layers stack portions at the sides of the central gate is formed with an “L” shape, with a base charge-confining layers stack portion lying on the substrate surface and an upright charge-confining layers stack portion lying against a respective side of the insulated gate.

摘要翻译： 一种用于制造双电荷存储位置电可编程存储单元的方法，包括在半导体衬底上形成中心绝缘栅极的步骤; 形成物理上分离的电荷限制层，堆叠在中心栅极侧的介质电荷捕获材料 - 电介质层堆叠部分，每个电荷限制层堆叠部分中的电荷捕获材料层形成电荷存储元件; 在每个电荷限制层堆叠部分上形成侧面控制栅极; 在侧控制门侧面形成存储单元源极/漏极区; 并将侧面控制门电连接到中央门。 在中心栅极侧面的电荷限制层堆叠部分中的每一个形成为“L”形，基底电荷限制层堆叠部分位于衬底表面上，并且垂直电荷限制层堆叠部分抵靠 绝缘门的相应侧。

公开(公告)号：US06365456B1

公开(公告)日：2002-04-02

申请号：US09507777

申请日：2000-02-18

申请人： Manlio Sergio Cereda ,  Claudio Brambilla ,  Paolo Caprara

发明人： Manlio Sergio Cereda ,  Claudio Brambilla ,  Paolo Caprara

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L21/0337 ,  H01L29/66825

摘要： A process for manufacturing electronic semiconductor integrated memory devices having a virtual ground and comprising at least a matrix of floating gate memory cells is presented. In the memory device, the matrix is formed on a semiconductor substrate with a number of continuous bit lines extending across the substrate as discrete parallel strips. The process begins by growing an oxide layer over the matrix region and depositing over the semiconductor throughout a stack structure which comprises a first conductor layer, a first dielectric layer, and a second conductor layer. Then a second dielectric layer is deposited over the stack structure, and floating gate regions are defined by photolithography using a mask of “POLY1 along a first direction”, to thereby define in the dielectric layer, a plurality of parallel strips which delimit a first dimension of floating gate regions. Next the dielectric layer is etched away to define a plurality of parallel dielectric strips and a number of dielectric islands are defined by photolithography using a mask of “POLY1 along a second direction” in the plurality of parallel strips. The dielectric layer is etched to define the plurality of islands. Finally, the stack structure and the thin gate oxide layer are etched to define gate regions of the matrix cells using said oxide island.

摘要翻译： 本发明提供一种制造具有虚拟接地并且至少包括浮动栅极存储单元矩阵的电子半导体集成存储器件的工艺。 在存储器件中，矩阵形成在半导体衬底上，多个连续的位线作为离散的平行条延伸穿过衬底。 该过程开始于在矩阵区域上生长氧化物层并且在包括第一导体层，第一介电层和第二导体层的整个堆叠结构中沉积在半导体上。 然后在堆叠结构上沉积第二介电层，并且通过使用“POLY1沿着第一方向”的掩模的光刻法定义浮动栅极区域，从而在电介质层中限定多个平行的条，其限定第一维度 的浮动门区域。 接下来，蚀刻掉电介质层以限定多个平行的介质条，并且通过使用在多个平行条带中的沿着第二方向的“POLY1”的掩模的光刻来限定多个介电岛。 蚀刻介电层以限定多个岛。 最后，使用所述氧化物岛蚀刻所述堆叠结构和所述薄栅极氧化物层以限定所述矩阵单元的栅极区域。