公开(公告)号：US20240363426A1

公开(公告)日：2024-10-31

申请号：US18770349

申请日：2024-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yu Yang ,  Yen-Ting Chen ,  Wei-Yang Lee ,  Fu-Kai Yang ,  Yen-Ming Chen

IPC: H01L21/8234 ,  H01L21/033 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823468 ,  H01L21/0337 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823864 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate, at least two gate structures disposed over the substrate, each of the at least two gate structures including a gate electrode and a spacer disposed along sidewalls of the gate electrode, wherein the spacer includes a refill portion and a bottom portion, the refill portion of the spacer has a funnel shape such that a top surface of the refill portion of the spacer is larger than a bottom surface of the refill portion of the spacer, and a source/drain contact disposed over the substrate and between the spacers of the at least two gate structures.

公开(公告)号：US20240355670A1

公开(公告)日：2024-10-24

申请号：US18756269

申请日：2024-06-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC NANJING COMPANY, LIMITED

Inventor： Min Han HSU ,  Chun-Chang CHEN ,  Jung-Chih TSAO

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/285 ,  H01L21/288 ,  H01L21/311 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76807 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/28568 ,  H01L21/2885 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76873 ,  H01L21/76877 ,  H01L23/5283 ,  H01L23/53228

Abstract: A semiconductor device includes a connector layer; a dielectric layer over the connector layer; and a conductive element in the dielectric layer, the conductive element including: a first region having a first uniform width; a second region having a second uniform width, wherein the second uniform width is less than the first uniform width; and a shoulder between the first region and the second region, wherein an angle of the shoulder relative to a top surface of the connector layer is greater than 20 degrees and less than 70 degrees.

公开(公告)号：US20240355633A1

公开(公告)日：2024-10-24

申请号：US18762702

申请日：2024-07-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Yen Chen

IPC: H01L21/308 ,  H01L21/033 ,  H01L21/306 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768

CPC classification number: H01L21/3086 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/30604 ,  H01L21/3088 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816

Abstract: A method includes forming an etching mask to cover a mandrel, a first spacer, and a second spacer, and the first spacer and the second spacer are in contact with opposing sidewalls of the mandrel. The etching mask is then patterned, and includes a first portion covering the first spacer, a second portion covering the second spacer, and a bridge portion connecting the first portion to the second portion. The bridge portion has first sidewalls. A first etching process is performed on the mandrel using the etching mask to define pattern, and after the first etching process, the mandrel includes a second bridge portion having second sidewalls vertically aligned to corresponding ones of the first sidewalls. After the mandrel is etched-through, a second etching process is performed to laterally recess the second bridge portion of the mandrel.

公开(公告)号：US20240355632A1

公开(公告)日：2024-10-24

申请号：US18638335

申请日：2024-04-17

Applicant: SHIN-ETSU CHEMICAL CO., LTD.

Inventor： Yasuyuki YAMAMOTO ,  Tomohiro IMATA ,  Daisuke KORI

IPC: H01L21/308 ,  G03F7/09 ,  H01L21/027 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L21/3081 ,  G03F7/094 ,  H01L21/0275 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32139

Abstract: The present invention is a composition for forming an organic film, comprising: a resin for forming an organic film; a polymer having a unit represented by the general formula (I), and at least one of a unit represented by the general formula (II) and a unit represented by the general formula (III); and a solvent, wherein the unit represented by the general formula (I), and at least one of the unit represented by the general formula (II) and the unit represented by the general formula (III) form a random copolymer, and the polymer has a fluorine content of 5 mass % to 16 mass %. This provides: a composition for forming an organic film that has excellent film-formability on a substrate and filling characteristics, and that inhibits humps in EBR process; and a method for forming an organic film, and patterning process using this composition.

公开(公告)号：US12125800B2

公开(公告)日：2024-10-22

申请号：US17683474

申请日：2022-03-01

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chun-Yen Wei

IPC: H01L23/544 ,  H01L21/768 ,  H01L23/522 ,  H01L21/027 ,  H01L21/033

CPC classification number: H01L23/544 ,  H01L21/76802 ,  H01L23/5226 ,  H01L21/0274 ,  H01L21/0337 ,  H01L2223/54426

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate, a first conductive feature, a first light-emitting feature, a first pattern and a second pattern. The first light-emitting feature is disposed on the substrate. The first pattern is disposed on the first light-emitting feature. The second pattern is disposed on the first pattern. The first conductive feature is disposed on the substrate and at least laterally overlaps the first pattern. The first light-emitting feature is configured to emit a light of a first wavelength. The first pattern has a first transmittance to the light of the first wavelength. The second pattern has a second transmittance to the light of the first wavelength. The first transmittance is different from the second transmittance.

公开(公告)号：US12112979B2

公开(公告)日：2024-10-08

申请号：US17833839

申请日：2022-06-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yan-Jhi Huang ,  Yu-Yu Chen

IPC: H01L21/76 ,  H01L21/033 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76829 ,  H01L21/76877

Abstract: A method for manufacturing a semiconductor device includes forming a hard mask layer overlying a device layer of a semiconductor device, a mandrel underlayer over hard mask layer, and a mandrel layer over mandrel underlayer. The mandrel layer has a plurality of mandrel lines extending along a first direction. A plurality of openings are formed in mandrel underlayer extending in a second direction substantially perpendicular to first direction. A spacer layer is formed over mandrel underlayer and layer. Spacer layer fills plurality of openings in underlayer. Portions of spacer layer are removed to expose an upper surface of underlayer and mandrel layer, and mandrel layer is removed. By using remaining portions of spacer layer as a mask, underlayer and hard mask layer are removed, to form a hard mask pattern with first hard mask pattern lines extending along first direction and second hard mask pattern lines extending along second direction.

公开(公告)号：US12106963B2

公开(公告)日：2024-10-01

申请号：US18140425

申请日：2023-04-27

Applicant: Tessera LLC

Inventor： Sean D. Burns ,  Lawrence A. Clevenger ,  Matthew E. Colburn ,  Nelson M. Felix ,  Sivananda K. Kanakasabapathy ,  Christopher J. Penny ,  Roger A. Quon ,  Nicole A. Saulnier

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528 ,  H01L21/027 ,  H01L21/28 ,  H01L21/31 ,  H10K71/20 ,  H10N70/00

CPC classification number: H01L21/0337 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76816 ,  H01L23/528 ,  H01L21/0274 ,  H01L21/28123 ,  H01L21/31 ,  H01L21/76897 ,  H01L2224/0362 ,  H01L2224/11622 ,  H10K71/233 ,  H10N70/063

Abstract: A method of forming a structure for etch masking that includes forming first dielectric spacers on sidewalls of a plurality of mandrel structures and forming non-mandrel structures in space between adjacent first dielectric spacers. Second dielectric spacers are formed on sidewalls of an etch mask having a window that exposes a connecting portion of a centralized first dielectric spacer. The connecting portion of the centralized first dielectric spacer is removed. The mandrel structures and non-mandrel structures are removed selectively to the first dielectric spacers to provide an etch mask. The connecting portion removed from the centralized first dielectric spacer provides an opening connecting a first trench corresponding to the mandrel structures and a second trench corresponding to the non-mandrel structures.

公开(公告)号：US12100594B2

公开(公告)日：2024-09-24

申请号：US17595589

申请日：2021-03-12

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： ChihCheng Liu

IPC: H01L21/033 ,  H01L21/265 ,  H01L21/266 ,  H10B12/00

CPC classification number: H01L21/0338 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/26513 ,  H01L21/266 ,  H10B12/00

Abstract: An active region array formation method is provided, including: providing a substrate, and forming a first hard mask layer on a surface of the substrate; patterning the first hard mask layer by using a composite etching process to form an active region shielding layer in the first hard mask layer, a pattern of the active region shielding layer being matched with a pattern of a to-be-formed active region array, wherein the composite etching process includes at least two patterning processes and at least one pattern transfer process; removing the remaining first hard mask layer; and forming the active region array in the substrate through the active region shielding layer.

公开(公告)号：US20240315018A1

公开(公告)日：2024-09-19

申请号：US18676056

申请日：2024-05-28

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Kunal R. Parekh ,  Martin C. Roberts ,  Mohd Kamran Akhtar ,  Chet E. Carter ,  David Daycock

IPC: H10B41/35 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3215 ,  H01L21/67 ,  H01L21/768 ,  H10B20/00 ,  H10B41/20 ,  H10B41/23 ,  H10B41/27 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/35 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/3215 ,  H01L21/32155 ,  H01L21/67063 ,  H01L21/76802 ,  H10B20/383 ,  H10B41/20 ,  H10B41/23 ,  H10B41/27 ,  H10B43/27 ,  H01L2221/1063 ,  H10B43/35

Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US12094712B2

公开(公告)日：2024-09-17

申请号：US17416527

申请日：2019-12-18

Applicant: INL—International Iberian Nanotechnology Laboratory

Inventor： Diego Colombara

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/32

CPC classification number: H01L21/0337 ,  H01L21/31144 ,  H01L21/32

Abstract: A method for patterning a surface of a substrate includes applying a liquid on the surface of the substrate, wherein an apparent viscosity of the liquid depends on a field strength applied to the liquid; applying a field to the liquid, wherein a field strength of the applied field is spatially varied in the liquid in a direction parallel to the surface of the substrate, thereby generating a spatially varied apparent viscosity distribution in the liquid in response to the applied field; and patterning the surface of the substrate by subjecting the surface to a surface modifying process, while maintaining the field and using portions of the liquid having apparent viscosities higher than a predetermined value as a mask; wherein the surface modifying process comprises removing material of the surface of the substrate and/or depositing material on the surface of the substrate.