公开(公告)号：US07105399B1

公开(公告)日：2006-09-12

申请号：US11004951

申请日：2004-12-07

申请人： Srikanteswara Dakshina-Murthy ,  Douglas Bonser ,  Hans Van Meer ,  David Brown

发明人： Srikanteswara Dakshina-Murthy ,  Douglas Bonser ,  Hans Van Meer ,  David Brown

IPC分类号： H01L21/302 ,  H01L21/8238

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/84

摘要： Gate electrodes with selectively tuned channel thicknesses are formed by selective epitaxial growth. Embodiments include forming shallow trench isolation regions in an SOI substrate, selectively removing the nitride stop layer and pad oxide layer in an exposed particular active region, and implementing selective epitaxial growth to increase the thickness of the semiconductor layer in the particular active region. Subsequently, the remaining nitride stop and pad oxide layers in other active regions are removed, gate dielectric layers formed, as by thermal oxidation, and the transistors completed.

摘要翻译： 通过选择性外延生长形成具有选择性调谐的沟道厚度的栅极。 实施例包括在SOI衬底中形成浅沟槽隔离区域，选择性地去除暴露的特定有源区域中的氮化物阻挡层和衬垫氧化物层，以及实现选择性外延生长以增加特定有源区域中的半导体层的厚度。 随后，去除其它有源区中剩余的氮化物阻挡层和焊盘氧化物层，如通过热氧化形成栅介电层，并完成晶体管。