公开(公告)号：USD1038234S1

公开(公告)日：2024-08-06

申请号：US29882739

申请日：2023-01-18

Applicant: David Tran

Designer： David Tran

Abstract: FIG. 1 is an isometric perspective view of embodiment 1 of a stationary holder with cat motif;
FIG. 2 is a front elevation view thereof;
FIG. 3 is a rear elevation view thereof;
FIG. 4 is a left side elevation view thereof;
FIG. 5 is a right side elevation view thereof;
FIG. 6 is a top plan view thereof; and
FIG. 7 is a bottom plan view thereof.
FIG. 8 is an isometric perspective view of embodiment 2;
FIG. 9 is a front elevation view of embodiment 2;
FIG. 10 is a rear elevation view of embodiment 2;
FIG. 11 is left side elevation of embodiment 2;
FIG. 12 is right side elevation of embodiment 2;
FIG. 13 is a top plan view of embodiment 2; and,
FIG. 14 is a bottom plan view of embodiment 2.
The broken lines shown in the drawings represent portions of the stationary holder with cat motif that form no part of the claimed design.

公开(公告)号：US08819094B2

公开(公告)日：2014-08-26

申请号：US12488956

申请日：2009-06-22

Applicant: Kyung-Nam Han ,  Alexandre Tenca ,  David Tran ,  Rick Kelly

Inventor： Kyung-Nam Han ,  Alexandre Tenca ,  David Tran ,  Rick Kelly

IPC: G06F7/38

CPC classification number: G06F7/535 ,  G06F2207/5355

Abstract: The technology is a division circuit with decreased circuit area. An embodiment includes an integrated circuit implementing multiplicative division of a dividend input and a divisor input. The integrated circuit includes a lookup table circuit and multiplier circuits. The lookup table circuit providing an approximation of a reciprocal of a divisor input. The multiplier circuits receive the approximation and refine a quotient output of the dividend input and a divisor input. At least one of the multiplier circuits is a squaring circuit implementing multiplication with a reduced number of intermediate partial products. The reduced number of intermediate partial products prevent the squaring circuit from multiplication of any two unequal numbers and limiting the squaring circuit to multiplication of a same number by the same number.

Abstract translation: 该技术是电路面积减小的分频电路。 实施例包括实现分红输入和除数输入的乘法除法的集成电路。 集成电路包括查找表电路和乘法器电路。 查找表电路提供除数输入的倒数的近似值。 乘法器电路接收近似值并优化除数输入的商输出和除数输入。 乘法器电路中的至少一个是实现与减少数量的中间部分乘积相乘的平方电路。 减少的中间部分积的数量防止平方电路与任何两个不相等的数字相乘，并且将平方电路限制为相同数量的乘法相同的数字。

公开(公告)号：US20100318592A1

公开(公告)日：2010-12-16

申请号：US12488956

申请日：2009-06-22

Applicant: Kyung-Nam Han ,  Alexandre Tenca ,  David Tran ,  Rick Kelly

Inventor： Kyung-Nam Han ,  Alexandre Tenca ,  David Tran ,  Rick Kelly

IPC: G06F7/52 ,  G06F17/50

CPC classification number: G06F7/535 ,  G06F2207/5355

Abstract: The technology is a division circuit with decreased circuit area. An embodiment includes an integrated circuit implementing multiplicative division of a dividend input and a divisor input. The integrated circuit includes a lookup table circuit and multiplier circuits. The lookup table circuit providing an approximation of a reciprocal of a divisor input. The multiplier circuits receive the approximation and refine a quotient output of the dividend input and a divisor input. At least one of the multiplier circuits is a squaring circuit implementing multiplication with a reduced number of intermediate partial products. The reduced number of intermediate partial products prevent the squaring circuit from multiplication of any two unequal numbers and limiting the squaring circuit to multiplication of a same number by the same number.

Abstract translation: 该技术是电路面积减小的分频电路。 实施例包括实现分红输入和除数输入的乘法除法的集成电路。 集成电路包括查找表电路和乘法器电路。 查找表电路提供除数输入的倒数的近似值。 乘法器电路接收近似值并优化除数输入的商输出和除数输入。 乘法器电路中的至少一个是实现与减少数量的中间部分乘积相乘的平方电路。 减少的中间部分积的数量防止平方电路与任何两个不相等的数字相乘，并且将平方电路限制为相同数量的乘法相同的数字。

公开(公告)号：US06356315B1

公开(公告)日：2002-03-12

申请号：US09165036

申请日：1998-10-01

Applicant: Chih-Kang Chen ,  Anil Sawe ,  David Tran

Inventor： Chih-Kang Chen ,  Anil Sawe ,  David Tran

IPC: H04N716

CPC classification number: G06T3/4023 ,  H04N5/14 ,  H04N5/2628 ,  H04N5/45 ,  H04N7/0102

Abstract: Magnification/reduction is achieved by a single FIR filter under the control of a Digital Differential Analyzer (DDA) as would be used to simulate a perfectly straight line on a two-dimensional raster. The single FIR filter combines the processes of interpolation, filter, and decimation. The DDA is programmed with the desired magnification/reduction ratio and provides signals that control shifting of input samples into the FIR filter and selection of FIR coefficients for the FIR filter.

Abstract translation: 在数字差分分析仪（DDA）的控制下，通过单个FIR滤波器实现放大/缩小，这将用于模拟二维光栅上的完美直线。 单个FIR滤波器组合了插值，滤波和抽取的过程。 DDA以所需的放大/缩小比率编程，并提供控制输入样本向FIR滤波器移位的信号，并为FIR滤波器选择FIR系数。

公开(公告)号：US6055811A

公开(公告)日：2000-05-02

申请号：US60666

申请日：1998-04-15

Applicant: James B. Maddock ,  Fred Mehdian ,  David Tran

Inventor： James B. Maddock ,  Fred Mehdian ,  David Tran

IPC: F02B37/18 ,  F02B37/22 ,  F02D41/00 ,  F02D23/00

CPC classification number: F02B37/225 ,  F02B37/18 ,  Y02T10/144

Abstract: The present invention includes a method and apparatus for controlling the air flow into an engine. The engine has a wastegate and a choke valve. The method includes the steps of determining an air pressure within the intake manifold and comparing the air pressure to a desired air pressure. A position of the choke valve and wastegate is then determined in response to the comparison. The apparatus includes an air pressure sensor for sensing the actual air pressure within the intake manifold. A controlling means compares the actual air pressure with a desired air pressure and responsively determines a position of the choke valve and the wastegate. A choke valve actuator and wastegate actuator position the choke valve and the wastegate respectively.

Abstract translation: 本发明包括一种用于控制进入发动机的空气流的方法和装置。 发动机有一个废气门和一个节流阀。 该方法包括以下步骤：确定进气歧管内的空气压力并将空气压力与期望的空气压力进行比较。 然后响应于比较来确定阻流阀和废气门的位置。 该装置包括用于感测进气歧管内的实际空气压力的空气压力传感器。 控制装置将实际空气压力与期望的空气压力进行比较，并且响应地确定阻流阀和废气门的位置。 阻流阀致动器和废气门执行器分别定位阻流阀和废气门。